Figure 7-2. Clock Timing
1A
1C
EXTAL
(INPUT)
VOLTAGE MIDPOINT
1
5C
5B
CLKO1
(OUTPUT)
2
3
4
5
5D
CLKO2
(OUTPUT)
3A
4A
2A
5A
7.6
External Capacitor For PLL
Table 7-5.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary.
Characteristic
Symbol
Min
Max
Unit
PLL External Capacitor (XFC to VCCSYN)
MF< 5 (Recommended value MF x 400 pF)(1)
MF> 4 (Recommended value MF x 540 pF)(1)
cXFC
MF x 340
MF x 380
MF x 480
MF x 970
pF
pF
Note:
1. MF – multiplication factor.
7.6.1
Examples:
Notes: 1. MODCK1 pin = 0, MF = 1 ⇒ CXFC = 400 pF
2. MODCK1 pin = 1, crystal is 32.768 kHz (or 4.192 MHz), initial MF = 401, initial frequency =
13.14 MHz, later on MF is changed to 762 to support a frequency of 25 MHz. Minimum CXFC
is: 762 x 380 = 289 nF, Maximum CXFC is: 401 x 970 = 390 nF. The recommended CXFC for 25
MHz is: 762 x 540 = 414 nF. 289 nF < CXFC < 390 nF and closer to 414 nF. The proper avail-
able value for CXFC is 390 nF.
3. MODCK1 pin = 1, crystal is 32.768 kHz (or 4.192 MHz), initial MF = 401, initial frequency =
13.14 MHz, later on MF is changed to 1017 to support a frequency of 33.34 MHz. Minimum
CXFC is: 1017 x 380 = 386 nF, Maximum CXFC is: 401 x 970 = 390 nF ⇒ 386 nF < CXFC < 390
nF. The proper available value for CXFC is 390 nF.
4. In order to get higher range, higher crystal frequency can be used (i.e. 50 kHz), in this case:
Minimum CXFC is: 667 x 380 = 253 nF, Maximum CXFC is: 401 x 970 = 390 nF ⇒ 386 nF <
CXFC < 390 nF.
18
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
