Table 7-6.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-3 to Figure 7-19) (Continued)
25 MHz
Min
33.34 MHz
Number
20
Characteristic
Symbol
tCHRL
tRAAA
tRACA
tRASA
tCHDO
tCHPV
tPVCL
Max
20
–
Min
Max
15
–
Unit
ns
CLKO1 High to R/W Low
R/W High to AS, CSx, OE Asserted
R/W High to CSx Asserted
R/W Low to DS Asserted (Write)
CLKO1 High to Data-Out
CLKO1 High to Parity Valid
Parity Valid to CAS Low
3
10
30
47
–
3
21(10)
21A(11)
22
7.5
ns
–
–
ns
–
36
–
–
ns
23
23
25
–
18
20
–
ns
23A
–
–
ns
23B
3
3
ns
Data-Out, Parity-Out Valid to Negating Edge of AS,
CSx, WE, (Fast Termination Write)
24(12)
25(12)
tDVASN
tSNDOI
tCNDOI
10
10
35
–
–
–
7.5
7.5
25
–
–
–
ns
ns
ns
DS, CSX, WE Negated to Data-Out, Parity-Out
Invalid (Data-Out, Parity-Out Hold)
CSx Negated to Data-Out, Parity-Out Invalid (Data-
Out, Parity-Out Hold)
25A(13)
26
Data-Out, Parity-Out Valid to DS Asserted (Write)
Data-In, Parity-In to CLKO1 Low (Data-Setup)
Data-In, Parity-In Valid to CLKO1 Low (Data-Setup)
tDVSA
tDICL
tDICL
10
1
–
–
–
7.5
1
–
–
–
ns
ns
ns
27(15)
27B(14)
20
15
Late BERR, HALT, BKPT Asserted to CLKO1 Low
(Setup Time)
27A
tBELCL
tSNDN
10
0
–
7.5
0
–
ns
ns
AS, DS Negated to DSACKx, BERR, HALT
Negated
28(18)
50
37.5
DS, CSx, OE, Negated to Data-In Parity-In Invalid
(Data-In, Parity-In Hold)
29(4)
29A(4)
30(4)
tSNDI
tSHDI
tCLDI
0
–
–
40
–
0
–
–
30
–
ns
ns
ns
DS, CSx, OE Negated to Data-In High Impedance
CLKO1 Low to Data-In, Parity-In Invalid (Fast
Termination Hold)
10
7.5
30A(4)
31(5)(15)
31A
31B(5)(14)
32
CLKO1 Low to Data-In High Impedance
DSACKx Asserted to Data-in, Parity-In Valid
DSACKx Asserted to DSACKx Valid (Skew)
DSACKx Asserted to Data-in, Parity-In Valid
HALT an RESET Input Transition Time
CLKO1 High to BG Asserted
tCLDH
tDADI
tDADV
tDADI
tHRrf
–
–
60
32
10
35
140
20
20
–
–
–
45
24
7.5
26
ns
ns
–
–
ns
–
–
ns
–
–
ns
33
tCLBA
tCLBN
tBRAGA
tGAGN
tGH
–
–
15
15
–
ns
34
CLKO1 High to BG Negated
–
22.5
1
ns
35(6)
BR Asserted to BG Asserted (RMC Not Asserted)
BGACK Asserted to BG Negated
BG Width Negated
1
CLKO1
CLKO1
CLKO1
CLKO1
ns
37
1
2.5
–
1
2.5
–
39
2
2
39A
46
BG Width Asserted
tGA
1
–
1
–
R/W Width Asserted (Write or Read)
tRWA
100
–
75
–
20
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
