TS68EN360
7.5
AC Electrical Specifications Control Timing
Table 7-4.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure
7-2)
25 MHz
Min
33.34 MHz
Number Characteristic
System Frequency
Symbol
fsys
Max
25.00
6000
50
Min
Max
Unit
MHz
kHz
dc(1)
33.34
6000
67
Crystal Frequency
fXTAL
fsys
25
25
20
On-Chip VCO System Frequency
20
MHz
Start-up Time
tpll
2500
clks
With external clock (oscillator disabled) or after
changing the multiplication factor MF
CLKO1-2 stability
∆
TBD
40
40
40
19
9.5
–
TBD
–
%
ns
%
CLK
1
1A
CLKO1 Period
tcyc
tdcyc
tEXTcyc
tCW1
30
40
30
14
7
–
60
–
EXTAL Duty Cycle, MF
60
–
1C
External Clock Input Period
ns
ns
ns
ns
ns
ns
ns
ns
2, 3
2A, 3A
4, 5
4A, 5A
5B
CLKO1 Pulse Width (Measured at 1.5V)
CLKO2 Pulse Width (Measured at 1.5V)
CLKO1 Rise and Fall Times (Full drive)
CLKO2 Rise and Fall Times (Full drive)
EXTAL to CLKO1 Skew-PLL enabled (MF< 5)
EXTAL to CLKO2 Skew-PLL enabled (MF< 5)
CLKO1 to CLKO2 Skew
–
–
tCW2
–
–
tCrf1
2
–
2
tCrf2
–
2
–
1.6
a
tEXTP1
tEXTP2
AtmelKW
a
5C
a
a
5D
a
a
Note:
1. Note that the minimum VCO frequency and the PLL default values put some restrictions on the minimum system frequency.
The following calculation should be used to determine the actual value for specifications 5B, 5C and 5D.
5B: 25 MHz
33 MHz
±(0.9 ns + 0.25 x (rise time)) (1.4 ns at rise = 2 ns; 1.9 ns at rise = 4 ns)
±(0.5 ns + 0.25 x (rise time)) (1 ns at rise = 2 ns; 1.5 ns at rise = 4 ns)
±(2 ns + 0.25 x (rise time)) (2.5 ns at rise = 2 ns; 3 ns at rise = 4 ns)
±(3 ns + 0.5 x (rise time)) (4 ns at rise = 2 ns; 5 ns at rise = 4 ns)
±(2.5 ns + 0.5 x (rise time)) (3.5 ns at rise = 2 ns; 4.5 ns at rise = 4 ns)
5C: 25/33 MHz
5D: 25 MHz
33 MHz
17
2113B–HIREL–06/05
ATMEL [ ATMEL ]
