This device contains protective circuitry against damage due to high static voltages or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any volt-
ages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation
is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or
VDD
)
Table 5-2.
Recommended Conditions of Use
Unless otherwise stated, all voltages are referenced to the reference terminal
Symbol
VCC
Parameter
Min
+4.75
GND
+2.0
-55
Typ
Max
+5.25
+0.8
VCC
Unit
V
Supply Voltage Range
VIL
Logic Low Level Input Voltage Range
Logic High Level Input Voltage Range
Operating Temperature
V
VIH
V
Tcase
VOH
+125
°C
High Level Output Voltage
+2.4
V
(For 25 MHz version)
(For 33 MHz version)
25
33
MHz
MHz
fsys
System Frequency
Table 5-3.
Symbol
Thermal Characteristics
Parameter
Value
2
Unit
240-pin Cerquad
241-pin PGA
θJC
Thermal Resistance - Junction to Case
Thermal Resistance - Junction to Ambient
°C/W
7
240-pin Cerquad
241-pin PGA
27.4
22.8
θJA
°C/W
TJ = TA + (PD · θJA)
PD = (VDD · IDD) + PI/O
Where PI/O is the power dissipation on pins.
5.3
Power Considerations
The average chip-junction temperature, TJ, in °C can be obtained from:
TJ = TA ÷ (PD · ΘJA) (1)
where:
TA = Ambient Temperature, °C
JA = Package Thermal Resistance,
Θ
Junction-to-Ambient, C/W
PD = PINT + P I/O
PINT = ICC · VCC, Watts-chip Internal Power
P
I/O = Power Dissipation on Input and Output Pins-User Determined
For most applications, PI/O < 0.3 · PINT and can be neglected.
12
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
