Table 1. System Bus Signal Index (Normal Operation) (Continued)
Group
Signal Name
Mnemonic
Function
Used to three-state all pins if QUICC is configured as a
master. Always Sampled except during system reset. (I)
Three-State
TRIS
Test Clock
TCK
TMS
Provides a clock for Scan test logic. (I)
Clock and Test
(Cont’d)
Test Mode Select
Test Data In
Controls test mode operations. (I)
TDI
Serial test instructions and test data signal. (I)
Serial test instructions and test data signal. (O)
Provides an asynchronous reset to the test controller. (I)
Power supply to the PLL of the clock synthesizer
Test Data Out
Test Reset
TDO
TRST
VCCSYN
Clock Synthesizer Power
Clock Synthesizer
Ground
GNDSYN
Ground supply to the PLL of the clock synthesizer
Clock Out Power
Clock Out Ground
VCCCLK
GNDCLK
Power supply to clock out pins
Ground supply to clock out pins
Power
Special ground for fast AC timing on certain system bus
signals
Special Ground 1
Special Ground 2
GNDS1
GNDS2
Special ground for fast AC timing on certain system bus
signals
System Power Supply
and Return
VCC, GND
NC4-NC1
Power supply and return to the QUICC
Four no-connect pins
--
No Connect
Note:
1. I denotes input, O denotes output and I/O is input/output.
8
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
