TS68882
Table 7. AC Electrical Characteristics – Read and Write Cycles(1)
VCC = 5.0 VDC 10%; GND = 0 VDC; Tc = -55°C/+125°C or Tc = -40°C/+85°C (see Figure 7, Figure 8, Figure 9)
16.67 MHz 20 MHz 25 MHz 33.33 MHz
N°
6
Parameter
Min
15
15
50
10
10
Max
Min
Max
Min
Max
Min
5
Max
Unit
ns
Address valid to AS asserted(5)
Address valid to DS asserted (read)(5)
Address valid to DS asserted (write)(5)
AS negated to address invalid(6)
DS negated to address invalid(6)
10
10
50
10
10
5
5
6a
6b
7
5
ns
35
5
26
5
ns
ns
7a
5
5
ns
CS asserted to AS asserted or AS asserted
to CS asserted(9)
8
0
0
0
0
0
0
0
0
ns
ns
ns
CS asserted to DS asserted or DS asserted
to CS asserted (read)(9)
8a
8b
CS asserted to DS asserted or DS asserted
to CS asserted (write)(9)
30
25
20
15
9
AS negated to CS negated
10
10
15
15
35
10
10
10
10
30
5
5
5
5
ns
ns
ns
ns
ns
9a
DS negated to CS negated
R/W high to AS asserted (read)
R/W high to DS asserted (read)
R/W low to DS asserted (write)
10
5
5
10a
10b
5
5
25
25
AS negated to R/W low (read) or
AS negated to R/W high (write)
11
10
10
10
10
5
5
5
5
ns
ns
DS negated to R/W low (read) or
DS negated to R/W high (write)
11a
12
13
DS width asserted (write)
40
40
30
38
38
30
30
30
25
23
23
18
ns
ns
ns
ns
ns
DS width negated
13a
14
DS negated to AS asserted(4)
CS, DS asserted to data-out valid (read)(2)
DS negated to data-out invalid (read)
80
50
45
35
45
35
30
30
15
0
0
0
0
DS negated to data-out high impedance
(read)
16
ns
17
18
Data-in invalid to DS asserted (write)
DS negated to data-in invalid (write)
15
15
10
10
5
5
5
5
ns
ns
START true to DSACK0 and DSACK1
asserted(2)
19
19a
20
50
15
50
50
35
10
43
30
25
10
32
40
20
5
ns
ns
ns
ns
DSACK0 asserted to DSACK1 asserted
(skew)(7)
-15
-10
-10
DSACK0 or DSACK1 asserted to data-out
valid
17
30
START false to DSACK0 and DSACK1
negated(8)
21
11
2119A–HIREL–04/02
ATMEL [ ATMEL ]
