TS68882
Package
The macrocircuits are packaged in hermetically sealed ceramic packages which are
conform to case outlines of MIL-STD-1835 (when defined):
•
•
68-PIN SQ.PGA UP PAE Outline
68-PIN Ceramic Quad Flat Pack CQFP
The precise case outlines are described on Figure 23 and Figure 24.
Electrical
Characteristics
Table 2. Absolute Maximum Ratings
Symbol
VCC
Parameter
Test Conditions
Min
-0.3
-0.3
Max
+7.0
+7.0
Unit
V
Supply Voltage
Input Voltage
VI
V
TCASE = -55°C to
+125°C
PDMAX
0.75
W
Max Power Dissipation
Operating Temperature
M Suffix
V Suffix
-55
-40
-55
+125
+85
°C
°C
°C
°C
TCASE
TSTG
Storage Temperature
Lead Temperature
+150
+270
TLEADS
Max 5 sec. Soldering
Recommended Condition of
Use
Unless otherwise stated, all voltages are referenced to the reference terminal (see
Table 1).
Table 3. DC Electrical Characteristics
VCC = 5.0 VDC 10%; GND = 0 VDC; Tc = -55°C to +125°C
Symbol
VCC
TCASE
VIH
Parameter
Min
4.5
Max
5.5
Unit
V
Supply Voltage
Operating Temperature
-55
+125
VCC
0.8
°C
V
Input High Voltage
2.0
VIL
Input Low Voltage
GND - 0.3
V
IIN
Input Leakage Current at 5.5V CLK, RESET, R/W, A0-A4, CS, DS, AS, SIZE
HI-Z (Off state) Input Current at 2.4V/0.4V DSACK0, DSACK1, D0-D31
Output High Voltage (IOH = -400 µA)(1) DSACK0, DSACK1, D0-D31
Output Low Voltage (IOL = 5.3 mA)(1) DSACK0, DSACK1, D0-D31
Output Low Current (VOL = GND) SENSE
Power Dissipation
10
µA
µA
V
ITSI
20
VOH
VOL
IOL
2.4
0.5
500
0.75
20
V
µA
W
pF
pF
PD
CIN
Capacitance (VIN = 0, TA = 25°C, f = 1 MHz)(2)
CL
Output Load Capacitance
130
Notes: 1. Test load, see Figure 5.
2. Capacitance is periodically sampled rather than 100% tested.
7
2119A–HIREL–04/02
ATMEL [ ATMEL ]
