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5962-8946303YC 参数 Datasheet PDF下载

5962-8946303YC图片预览
型号: 5962-8946303YC
PDF下载: 下载PDF文件 查看货源
内容描述: [Math Coprocessor, CMOS, CQFP68, CERAMIC, QFP-68]
分类和应用: 外围集成电路
文件页数/大小: 43 页 / 1238 K
品牌: ATMEL [ ATMEL ]
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Table 7. AC Electrical Characteristics Read and Write Cycles(1) (Continued)  
CC = 5.0 VDC 10%; GND = 0 VDC; Tc = -55°C/+125°C or Tc = -40°C/+85°C (see Figure 7, Figure 8, Figure 9)  
V
16.67 MHz 20 MHz 25 MHz 33.33 MHz  
N°  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
START false to DSACK0 and DSACK1  
high impedance(8)  
22  
70  
55  
55  
40  
ns  
START true to clock high (synchronous  
read)(3)(8)  
23  
24  
25  
26  
27  
0
0
0
0
ns  
ns  
Clock low to data-out valid synchronous  
read)(3)  
105  
80  
60  
45  
START true to data-out valid (synchronous  
read)(3)(8)  
0
1.5  
105+  
2.5  
80 +  
2.5  
60+  
2.5  
45-  
2.5  
ns  
Clks  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
Clock low to DSACK0 and DSACK1  
asserted (synchronous read(3)  
75  
55  
45  
30  
ns  
START true to DSACK0 and DSACK1  
asserted (synchronous read) (3)(8)  
75+  
2.5  
55+  
2.5  
45+  
2.5  
30-  
2.5  
ns  
Clks  
1.5  
Notes: 1. Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted.  
The voltage swing through this range should start outside, and pass through, the range such that the rise or fall will be linear  
between 0.8V and 2.0V.  
2. These specifications only apply if the TS68882 has completed all internal operations initiated by the termination of the previ-  
ous bus cycle when DS was negated.  
3. Synchronous read cycles occur only when the save or response CIR locations are read.  
4. This specification only applies to systems in which back-to-back accesses (read-write or write-write) of the operand CIR can  
occur. When the TS68882 is used as a co-processor to the TS68020/68030, this can occur when the addressing mode is  
immediate.  
5. If the SIZE pin is not strapped to either VCC or GND, it must have the same setup times as do addresses.  
6. If the SIZE pin is not strapped to either VCC or GND, it must have the same hold times as do addresses.  
7. This number is reduced to 5 nanoseconds if DSACK0 and DSACK1 have equal loads.  
8. START is not an external signal; rather, it is the logical condition that indicates the start of an access. The logical equation for  
this condition is START = CS + AS + (R/W · DS).  
9. If a subsequent access is not a FPCP access, CS must be negated before the assertion of AS and/or DS on the non-FPCP  
access. These specifications replace the old specifications 8 and 8A (the old specifications implied that in all cases, transi-  
tions in CS must not occur simultaneously with transitions of AS or DS. This is not a requirement of the TS68882).  
12  
TS68882  
2119AHIREL04/02