29C516E
Table 7: Single Bit Error
MD[..]
[15]
34
[14]
2A
[13]
29
[12]
25
[11]
32
[10]
1A
[9]
16
[8]
13
[7]
31
[6]
23
[5]
15
[4]
0B
[3]
2C
[2]
1C
[1]
0E
[0]
0D
SY
(hexa)
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
MC[..]
[–]
[–]
[5]
[4]
[3]
[2]
[1]
[0]
SY
(hexa)
––
h
––
h
20
10
08
04
02
01
h
h
h
h
h
h
8.3. Double–Bit Error
If two errors occur, there will be 2, 3, 4, 5, 6 or 8 bits set activated to indicate that errors are present but cannot be
to one in the syndrome byte. The syndrome value corrected.
generated by a double–bit error does not take place of a Example: If MD[5] and MC[7] are incorrect, syndrome
syndrome value generated by a single–bit error. Then, bits [0], [2], [4] and [6] are set to one (SY=55h ), NCERR
only the non correctable error flag NCERR will be is set low and CERR remains at high level.
8.4. Triple–Bit Error
When three errors are detected, an error flag is set low as This is decoded by the 29C516E EDAC as being a
warning to the system. But the generated syndrome can correctable error on MD[10]. The CERR flag is set low
have the listed value of single–bit error. The device must and correction would take place if the device is in correct
be in detect mode to prevent false correction occurrence. mode. This would cause more errors.
Example: If MD[0], MD[9] and MC[0] are corrupted, the
syndrome value is ”1Ah ”.
8.5. 4–bit Wide Memory Error
The 8 check–bit code can be used to provide error A special attention must be taken, multi–bit error ( 3)
detection for up to 4 errors occur in the following groups: located into the defined groups can provide the syndrome
MD[15..12], MD[11..8], MD[7..4], MD[3..0], MC[7..4] byte of a single–bit error.
and MC[3..0]. The 29C516E EDAC can flag any number Example: If MD[11], MD[10], MD[9] and MD[8] are in
of errors in 4–bit wide memory chip.
error, the syndrome code is ”AD h ”.
8.6. 8–bit Wide Memory Error
The 8 check–bit code can be used to provide error can provide the syndrome byte of a single–bit error.
detection for up to 8 errors occurring in the following Example: If MD[13], MD[12], MD[10] and MD[9] are in
groups: MD[15..8], MD[7..0] and MC[7..0].
error, the syndrome code is ”40h ”. (In 6 check–bit
coding, the syndrome code should have been ”00h ”, the
”No Error Detected” value.) Note that the syndrome code
”40 h ” is also the code for MC[6] in error.
The 29C516E EDAC can flag any number of errors in
8–bit wide memory chip. A special attention must be
taken, multi–bit error ( 3) located into the defined groups
9. Transactions
Transactions Three types of transactions may be done:
9.1. Memory Read
The TRANS pin is driven at a high level to select the MEMx and ENx. All transaction managed by the master
access to the memory. The external arbiter drives the user can be listened by the second user.
U2/U1 pin and dispatches the commands RD/WRx,
9
Rev. E (03 2007)
ATMEL [ ATMEL ]
