29C516E
10. Signal Timing
10.1. Memory Write
Figure 4.Memory Write Timing Diagram
U2/U1
N22
t13
t20
t22
t22
t22
t20
t19
t23
t23
t23
t2
t3
MD[0..15]
Memory Data Word
t14
t20
1.5
t21
t23
t23
t23
t22
1.5
t22
t22
t20
2.5
MC[0..7]
Generated Check–bits
UD2[0..15]
TRANS
1.5
RD/WR2
EN2
MEM2
Propagation Delays
t2 *
t3 *
t13 *
t14 *
30 ns
( * : Max Value )
( * : Max Value )
13 ns
26 ns
18 ns
Output Enable /
Disable Times
t19 *
23 ns
t20 *
22 ns
t21 *
22 ns
t22 *
19 ns
Figure 5.Transfer Write Timing Diagram
U2/U1
t13
t20
t12
t22
t22
t22
t18
t21
t23
t23
t23
t19
t1
UD2[0..15]
UD1[0..15]
TRANS
RD/WR1
EN1
MEM1
Propagation Delays
t1 *
t12 *
20 ns
t13 *
18 ns
( * : Max Value )
14 ns
Output Enable /
Disable Times
t18 *
23 ns
t19 *
23 ns
t20 *
22 ns
t21 *
22 ns
t22 *
19 ns
t23 *
19 ns
( * : Max Value )
12
Rev. E (03 2007)
ATMEL [ ATMEL ]
