29C516E
Table 5: 8–Bit Syndrome Word to Bit–In–Error (N22 = ”0”)
Hex
0
0
0
1
0
0
2
0
0
3
0
0
4
0
1
5
0
1
6
0
1
7
0
1
8
1
0
9
1
0
A
1
B
1
C
1
D
1
E
1
F
1
7
6
0
0
1
1
1
1
Syndrome Bit
5
4
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
SY [..]
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Hex
0
N.E.D
MC0
MC1
D
MC4
D
MC5
D
D
D
M
D
D
D
D
M
M
D
D
M
D
M
M
D
MC6
D
D
D
D
D
D
MD7
D
MC7
D
D
M
M
M
D
D
D
D
D
M
D
M
D
D
D
M
D
D
D
M
D
D
M
M
D
M
D
M
D
D
D
1
D
D
D
D
D
D
D
D
D
MD11
D
2
D
MD6
D
D
MD8
M
D
D
D
D
D
D
D
M
D
3
MC2
D
D
D
M
M
M
D
M
M
M
D
D
D
MD15
D
M
D
D
D
4
M
D
D
D
MD12
M
MD5
M
D
D
5
D
MD9
D
M
D
D
D
D
D
M
D
D
6
M
D
M
D
D
M
D
D
M
M
D
M
M
D
D
M
M
D
7
MC3
D
D
D
M
M
D
D
D
D
D
D
8
M
M
D
D
D
M
M
M
D
D
M
MD13
M
D
9
D
MD10 MD14
D
D
D
D
D
D
M
D
A
B
C
D
E
F
D
D
M
D
D
D
D
D
M
MD4
D
D
D
D
M
M
D
D
M
M
D
D
D
M
M
M
M
M
M
M
M
MD3
D
D
MD2
D
D
MD0
M
D
D
D
M
M
D
M
MD1
D
D
M
M
D
D
D
D
D
D
D
D
D
M
D
M
D
M
M
M
Note : N.E.D = No Errors Detected
MDx = Memory Data Bit–In–Error
MCx = Memory Check Bit–In–Error
D = Double–Bit–In–Error Detected
M = Multi–Bit–In–Error Detected
7. The 6–Bit Syndrome Word
This feature is available when the N22 pin is driven at a
high level.
7.1. No Errors
If there are no errors in the read Data or Check–Bit, all the
syndrome byte is ”00”. The EDAC flags are inactive.
No Error : SY=00
7.2. Single Bit–Error
A single bit–error in a Memory Data word read (MD[..]) Data word and provides the expected Data word for the
causes three syndrome bits to be set to one. The code EDAC controller.
formed indicates which bit of the Memory Data word is
incorrect.
If there is an error in the Memory Check–bit (MC[..]),
only one bit of the syndrome is set to one.
For example, if MD[2] were incorrect, the syndrome byte
In this case, the syndrome decoder sets low the
would have bits 2, 3 and 4 set to one. The syndrome
correctable error flag CERR, but NCERR does not
decoder of 29C516E EDAC decodes the information in
change. It does not correct the Check–bit because these
the syndrome byte and only sets low the error flag CERR.
bits are not used by the system.
In correct mode (CORRECT pin active), it inverts (and
hence corrects) the relevant bit in error of the Memory
7
Rev. E (03 2007)
ATMEL [ ATMEL ]
