Torwards
AT8563
faulty reading of the clock/calendar during a carry condition is prevented.
2.2 Alarm function modes
———
By clearing the MSB (bit AE= Alarm Enable) of one or more of the alarm registers, the
corresponding alarm condition(s) will be active. In this way an alarm can be generated from
once per minute up to once per week. The alarm condition sets the alarm flag, AF (bit 3 of
Control/Status 2 register). The asserted AF can be used to generate an interrupt (INT). Bit AF
can only be cleared by software.
2.3 Timer
The 8-bit countdown timer (address 0FH) is controlled by the Timer Control register
(address 0EH; see Table 25). The Timer Control register selects one of 4 source clock
frequencies for the timer (4096, 64, 1, or 1⁄60 Hz), and enables/disables the timer. The timer
counts down from a software-loaded 8-bit binary value. At the end of every countdown, the
timer sets the timer flag TF (see Table 7). The timer flag TF can only be cleared by software.
The asserted timer flag TF can be used to generate aninterrupt (INT). The interrupt may be
generated as a pulsed signal every countdownperiod or as a permanently active signal which
follows the condition of TF. TI/TP (seeTable 7) is used to control this mode selection. When
reading the timer, current countdown value is returned.
2.4 CLKOUT output
A programmable square wave is available at the CLKOUT pin. Operation is controlled by
the CLKOUT frequency register (address 0DH; see Table 23). Frequencies of 32.768 kHz
(default), 1024, 32 and 1 Hz can be generated for use as a system clock, microcontroller clock,
input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output
and enabled at power-on. If disabled it becomes high-impedance.
2.5 Reset
AT8563 includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I2C-bus logic is initialized and all registers, including the address
———
pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC and AEwhich are set
to logic 1.
2.6 Voltage-low detector
AT8563 has an on-chip voltage-low detector. When VDD drops below Vlow the VL bit
(Voltage Low, bit 7 in the Seconds register) is set to indicate that reliable clock/calendar
information is no longer guaranteed. The VL flag can only be cleared by software.
The VL bit is intended to detect the situation when VDD is decreasing slowly for example
under battery operation. Should VDD reach Vlow before power is re-asserted then the VL bit will
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