Torwards
AT8563
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
Fig 9 Acknowledge on the I2C -bus
3.2 I2C of AT8563
Before any data is transmitted on the I2C -bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after the
start procedure.
AT8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is
only an input signal, but the data signal SDA is a bidirectional line.
AT8563 slave address is shown in Fig 10.
Fig 10 Slave address
The I2C -bus configuration for the different AT8563 read and write cycles are shown in Fig
11, 12 and 13. The word address is a four bit value that defines which register is to be
accessed next. The upper four bits of the word address are not used.
Fig 11 Master transmits to slave receiver (write mode)
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