Torwards
AT8563
Fig 6 I2C-bus system configuration.
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the start condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop
condition (P); see Fig 7.
Fig 7 START and STOP conditions on the I2C-bus
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time will be
interpreted as a control signal; see Fig 8.
Fig 8 Bit transfer on the I2C-bus
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte. Also a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related
clock pulse (set-up and hold times must be taken into consideration).
A master receiver must signal an end of data to the transmitter by not generating an
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