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AT8563 参数 Datasheet PDF下载

AT8563图片预览
型号: AT8563
PDF下载: 下载PDF文件 查看货源
内容描述: [AT8563是一款经典的工业级实时时钟芯片(RTC),I2C总线接口,具有功耗低、精度高等特点,广泛应用于电表、水表、气表、电话等产品。]
分类和应用: 电话时钟
文件页数/大小: 24 页 / 729 K
品牌: Narda-ATM [ Narda-ATM ]
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Torwards  
AT8563  
Symbol  
Description  
0EH  
b1  
Timer source clock frequency selection bits. These bits  
determine the source clock for the countdown timer, see  
Table 26. When not in use, TD1 and TD0 should be set to  
‘11’ (160 Hz) for power saving.  
TD1  
b0  
TD0  
Table 26 Timer source clock frequency selection  
Timer source clock  
TD[1:0]  
frequencyHz)  
00  
01  
10  
11  
4096  
64  
1
1/60  
Table 27 Timer countdown value register bits description  
Description  
0FH  
Symbol  
<timer countdown value>  
b7b0  
countdown value n, the counter’s period is “”n/fCLK”  
2.8 EXT_CLK test mode  
A test mode is available which allows for on-board testing. In this mode it is possible to set  
up test conditions and control the operation of the RTC.  
The test mode is entered by setting bit TEST1 in the Control/Status1 register. The  
CLKOUT pin then becomes an input. The test mode replaces the internal 64 Hz signal with the  
signal that is applied to the CLKOUT pin. Every 64 positive edges applied to CLKOUT will then  
generate an increment of one second.  
The signal applied to the CLKOUT pin should have a minimum pulse width of 300 ns and  
a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is divided  
down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be set into a known  
state by using the STOP bit. When the STOP bit is set, the pre-scaler is reset to 0. STOP must  
be cleared before the pre-scaler can operate again. From a STOP condition, the first 1 s  
increment will take place after 32 positive edges on CLKOUT. Thereafter, every 64 positive  
edges will cause a 1 s increment.  
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.  
When entering the test mode, no assumption as to the state of the pre-scaler can be made.  
You can operate in the following steps:  
1. Enter the EXT_CLK test mode; set bit 7 of Control/Status 1 register (TEST = 1)  
2. Set bit 5 of Control/Status 1 register (STOP = 1)  
3. Clear bit 5 of Control/Status 1 register (STOP = 0)  
4. Set time registers (Seconds, Minutes, Hours, Days, Weekdays, Months/Century and  
Years) to desired value  
11  
深圳市宏达科技有限公司 Mobile:13530382140 曾先生  
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