AX88196
Local CPU BUS MAC Controller
6.4.7 MII Timing
Ttclk
Ttch Ttcl
TXCLK
Ttv
Tth
TXD<3:0>
TXEN
Trclk
Trch Trcl
RXCLK
RXD<3:0>
RXDV
Trs
Trh
Trs1
RXER
Symbol
Ttclk Cycle time(100Mbps)
Description
Min
-
-
14
140
14
140
-
5
-
-
14
140
14
140
6
Typ.
40
400
-
-
-
-
-
-
40
400
-
-
-
-
-
-
-
Max
-
-
26
260
26
260
20
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ttclk Cycle time(10Mbps)
Ttch
Ttch
Trch
Trch
Ttv
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
Clock to data valid
Data output hold time
Tth
Trclk Cycle time(100Mbps)
Trclk Cycle time(10Mbps)
-
-
Trch
Trch
Trcl
Trcl
Trs
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
data setup time
26
260
26
260
-
Trh
data hold time
10
10
-
-
Trs1
RXER data setup time
31
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ASIX [ ASIX ELECTRONICS CORPORATION ]
