AX88196
Local CPU BUS MAC Controller
6.4.6 8051 Bus Access Timing
/PSEN
Tsu(PSEN)
Th(PSEN)
Th(A)
Tsu(A)
SA[9:0],SAL,SAH
/IOWR,/IORD
Ten(RD)
Tw(RW)
Tv(RDY)
Tdis(RDY)
(For Reference)
RDY
Tdis(RD)
Read Data
SD[7:0](Dout)
DATA Valid
Tsu(WR)
Th(WR)
Write Data
SD[7:0](Din)
DATA Input Establish
Symbol
Tsu(A)
Description
ADDRESS SETUP TIME
Min
0
5
0
5
-
0.5
5
Typ.
Max
-
-
-
-
20
4
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
Th(A)
ADDRESS HOLD TIME
/PSEN SETUP TIME
/PSEN HOLD TIME
Tsu(PSEN)
Th(PSEN)
Ten(RD)
Tdis(RD)
Tsu(WR)
Th(WR)
OUTPUT ENABLE TIME FROM /IORD
OUTPUT DISABLE TIME FROM /IORD
DATA SETUP TIME
DATA HOLD TIME
5
-
Tw(RW)
/IORD OR /IOWR WIDTH TIME
*60
ns
Note : 60 ns at internal operation clock 20MHz.
50 ns at internal operation clock 25MHz.
30
ASIX ELECTRONICS CORPORATION
ASIX [ ASIX ELECTRONICS CORPORATION ]
