AX88196
Local CPU BUS MAC Controller
PAGE 1 (PS1=0,PS0=1)
OFFSET
READ
Command Register
( CR )
Physical Address Register 0
( PARA0 )
Physical Address Register 1
( PARA1 )
Physical Address Register 2
( PARA2 )
Physical Address Register 3
( PARA3 )
Physical Address Register 4
( PARA4 )
Physical Address Register 5
( PARA5 )
WRITE
Command Register
( CR )
Physical Address Register 0
( PAR0 )
Physical Address Register 1
( PAR1 )
Physical Address Register 2
( PAR2 )
Physical Address Register 3
( PAR3 )
Physical Address Register 4
( PAR4 )
Physical Address Register 5
( PAR5 )
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )
Multicast Address Register 7
( MAR7 )
10H, 11H
12H
Data Port
Inter-frame Gap Segment 1
IFGS1
Data Port
Inter-frame Gap Segment 1
IFGS1
13H
Inter-frame Gap Segment 2
IFGS2
Inter-frame Gap Segment 2
IFGS2
14H
15H
16H
17H
MII/EEPROM Access
-
Inter-frame Gap (IFG)
Reserved
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
Reserved
18H - 1AH Standard Printer Port (SPP)
1BH - 1EH Reserved
Standard Printer Port (SPP)
Reserved
1FH
Reset
Reserved
Tab - 11 Page 1 of MAC Core Registers Mapping
17
ASIX ELECTRONICS CORPORATION
ASIX [ ASIX ELECTRONICS CORPORATION ]
