AX88196
Local CPU BUS MAC Controller
4.1 Command Register (CR) Offset 00H (Read/Write)
FIELD NAME
DESCRIPTION
7:6
PS1,PS0 PS1,PS0 : Page Select
The two bit selects which register page is to be accessed.
PS1
0
0
PS0
0
1
page 0
page 1
5:3
RD2,RD1 RD2,RD1,RD0 : Remote DMA Command
,RD0 These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88196 when a Remote
DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA
has been aborted. The Remote Start Address are not restored to the starting address if the
Remote DMA is aborted.
RD2 RD1 RD0
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Not allowed
Remote Read
Remote Write
Not allowed
Abort / Complete Remote DMA
2
1
0
TXP TXP : Transmit Packet
This bit could be set to initiate transmission of a packet
START START :
This bit is used to active AX88196 operation.
STOP STOP : Stop AX88196
This bit is used to stop the AX88196 operation.
4.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)
FIELD NAME
DESCRIPTION
7
RST Reset Status :
Set when AX88196 enters reset state and cleared when a start command is issued to the
CR. Writing to this bit is no effect.
6
5
RDC Remote DMA Complete
Set when remote DMA operation has been completed
CNT Counter Overflow
Set when MSB of one or more of the Tally Counters has been set.
OVW OVERWRITE : Set when receive buffer ring storage resources have been exhausted.
TXE Transmit Error
4
3
Set when packet transmitted with one or more of the following errors
n
n
Excessive collisions
FIFO Underrun
2
RXE Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
FIFO Overrun
Missed Packet
1
0
PTX Packet Transmitted
Indicates packet transmitted with no error
PRX Packet Received
Indicates packet received with no error.
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