AX88196
Local CPU BUS MAC Controller
4.0 Registers Operation
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the
Command Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET
READ
Command Register
WRITE
Command Register
00H
( CR )
( CR )
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Status Register
( TSR )
Number of Collisions Register
( NCR )
Current Page Register
( CPR )
Interrupt Status Register
( ISR )
Current Remote DMA Address 0
( CRDA0 )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Page Start Address
( TPSR )
Transmit Byte Count Register 0
( TBCR0 )
Transmit Byte Count Register 1
( TBCR1 )
Interrupt Status Register
( ISR )
Remote Start Address Register 0
( RSAR0 )
Remote Start Address Register 1
( RSAR1 )
Remote Byte Count 0
( RBCR0 )
Remote Byte Count 1
( RBCR1 )
Receive Configuration Register
( RCR )
Current Remote DMA Address 1
( CRDA1 )
Reserved
Reserved
Receive Status Register
( RSR )
Frame Alignment Errors
( CNTR0 )
CRC Errors
( CNTR1 )
Transmit Configuration Register ( TCR )
Data Configuration Register
( DCR )
Interrupt Mask Register
( IMR )
Missed Packet Errors
( CNTR2 )
10H, 11H
12H
Data Port
IFGS1
Data Port
IFGS1
13H
IFGS2
IFGS2
14H
15H
MII/EEPROM Access
-
MII/EEPROM Access
Test Register
16H
17H
Inter-frame Gap (IFG)
Reserved
Inter-frame Gap (IFG)
Reserved
18H - 1AH Standard Printer Port (SPP)
1BH - 1EH Reserved
Standard Printer Port (SPP)
Reserved
1FH
Reset
Reserved
Tab - 10 Page 0 of MAC Core Registers Mapping
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