AX88196
Local CPU BUS MAC Controller
4.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
-
Reserved
RDCE DMA Complete Interrupt Enable. Default “low” disabled.
CNTE Counter Overflow Interrupt Enable. Default “low” disabled.
OVWE Overwrite Interrupt Enable. Default “low” disabled.
TXEE Transmit Error Interrupt Enable. Default “low” disabled.
RXEE Receive Error Interrupt Enable. Default “low” disabled.
PTXE Packet Transmitted Interrupt Enable. Default “low” disabled.
PRXE Packet Received Interrupt Enable. Default “low” disabled.
4.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD NAME
DESCRIPTION
7
6:2
1
RDCR Remote DMA always completed
Reserved
BOS Byte Order Select
-
0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80186).
1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(MC68K)
0
WTS Word Transfer Select
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
4.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD NAME
DESCRIPTION
7
FDU Full Duplex :
This bit indicates the current media mode is Full Duplex or not.
0 : Half duplex
1 : Full duplex
6
5
PD
Pad Disable
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
RLO Retry of late collision
0 : Don’ t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
Reserved
LB1,LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
4:3
2:1
-
Mode 0
Mode 1
Mode 2
0
0
1
0
1
0
Normal operation
Internel NIC loop-back
PHYcevisor loop-back
0
CRC Inhibit CRC
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
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