AS3525-A/-B C22O22
Data Sheet, Confidential
8.3.2 CTBGA144 Ball List
Table 162 CTBGA144 Ball List
Ball Nr.
Ball Name
PAD Type
I/O
Ball Description
BGA144
XRES
resetext_n
clk_ext
DO
D IN ST
D IN ST PD
O
I
I
XRES is generated by the PMU subsystem and connected to
reset input (active low) on the BGA
external clock input (10-26MHz)
K3
C2
I
clock select
D2
clk_sel
D IN ST PD
0 (low): clock from internal oscillator is used
1 (high): clock from pad clk_ext is used
test mode select
For testing purpose only, has to be set to “0”.
USB mini receptacle identifier
Has to be connected to USB jack ID pin.
I
I
E2
G3
tmsel
D IN ST PD
id_dig
D IN ST (PU)
Port A
xpa[0]
xpa[1]
xpa[2]
xpa[3]
xpa[4]
xpa[5]
xpa[6]
xpa[7]
D5
D6
C5
C6
B5
B6
A5
A6
D IO ST PD LSR IO GPIO IO, Port A
D IO ST PD LSR IO GPIO IO, Port A
D IO ST PD LSR IO GPIO IO, Port A
D IO ST PD LSR IO GPIO IO, Port A
D IO ST PD LSR IO GPIO IO, Port A
D IO ST PD LSR IO GPIO IO, Port A
D IO ST PD LSR IO GPIO IO, Port A
D IO ST PD LSR IO GPIO IO, Port A
Port B / DISPLAY / UART
IO GPIO IO, Port B
xpb[0]
I
static memory chip memory width setting for boot loader
mpmc_stcs1mw[0
]*
0: 8 bit data bus
1: 16 bit data bus
The value is latched at reset.
DISPLAY control output
G6
G5
D IO ST PD LSR
O
dbop_c0
xpb[1]
IO GPIO IO, Port B
I
static memory chip select polarity setting for boot loader
0: active LOW chip select
1: active high chip select
The value is latched at reset.
DISPLAY control output
D IO ST PD LSR
mpmc_stcs1pol*
O
dbop_c1
xpb[2]
IO GPIO IO, Port B
I
static memory byte lane polarity setting for boot loader
0: HIGH for reads, LOW for writes, used for we_n access
1: LOW for reads, LOW for writes, used for upper and lower byte
access
G4
D IO ST PD LSR
mpmc_stcs1pb*
The value is latched at reset.
O
DISPLAY control output
dbop_c2
xpb[3]
IO GPIO IO, Port B
I
test mode configuration (for testing purpose only !!!)
The value is latched at reset.
DISPLAY control output
H8
H7
D IO ST PD LSR
D IO ST PD LSR
mpmc_rel1config*
O
dbop_c3
xpb[4]
IO GPIO IO, Port B
IO DISPLAY data input/output (high byte)
IO GPIO IO, Port B
dbop_d[8]
xpb[5]
H6
H5
D IO ST PD LSR
D IO ST PU LSR
IO DISPLAY data input/output (high byte)
IO GPIO IO, Port B
dbop_d[9]
xpb[6]
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