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A3525BC21O22TRA 参数 Datasheet PDF下载

A3525BC21O22TRA图片预览
型号: A3525BC21O22TRA
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的音频处理器系统 [Advanced Audio Processor System]
分类和应用:
文件页数/大小: 194 页 / 3286 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS3525-A/-B C22O22  
Data Sheet, Confidential  
Ball Nr.  
Ball Name  
PAD Type  
I/O  
Ball Description  
BGA144  
ms_bs  
O
MEMORY STICK bus state  
xpd[6]  
IO GPIO IO, Port D  
mci_fbclk  
ms_fbclk  
xpd[7]  
I
I
MMC/SD feedback clock  
MEMORY STICK feedback clock  
G8  
G7  
D IO ST LSR  
D IO ST LSR  
IO GPIO IO, Port D  
mci_rod  
O
MMC/SD resistor open drain control  
2-WIRE SERIAL Audio Master  
O
O
2-WIRE SERIAL audio master clock line  
used for controlling the audio/PMU sub system  
2-WIRE SERIAL audio master data line  
J3  
CSCL  
CSDA  
D IO ST PU LSR  
D IO ST PU LSR  
K2  
used for controlling the audio/PMU sub system  
Serial Synchronous Port  
ssp_fssout  
O
I
SSP master, frame or slave select  
SSP slave, frame select  
SSP master, clock line  
B7  
B8  
D IO ST PU LSR  
ssp_fssin  
ssp_clkout  
ssp_clkin  
ssp_rxd  
O
I
D IO ST PU LSR  
SSP slave, clock line  
C7  
C8  
I
SSP receive data input  
SSP transmit data output  
D IO ST PU LSR  
D IO ST PU LSR  
ssp_txd  
O
NandFlash / IDE  
naf_d[0]  
IO NAND FLASH data line (low byte)  
IO NAND FLASH data line (low byte)  
IO NAND FLASH data line (low byte)  
IO NAND FLASH data line (low byte)  
IO NAND FLASH data line (low byte)  
IO NAND FLASH data line (low byte)  
IO NAND FLASH data line (low byte)  
IO NAND FLASH data line (low byte)  
IO NAND FLASH data line (high byte)  
IO NAND FLASH data line (high byte)  
IO NAND FLASH data line (high byte)  
IO NAND FLASH data line (high byte)  
IO NAND FLASH data line (high byte)  
IO NAND FLASH data line (high byte)  
A12  
A11  
D IO ST PD LSR  
D IO ST PD LSR  
naf_d[1]  
naf_d[2]  
naf_d[3]  
naf_d[4]  
naf_d[5]  
naf_d[6]  
naf_d[7]  
naf_d[8]  
naf_d[9]  
naf_d[10]  
naf_d[11]  
naf_d[12]  
naf_d[13]  
A10  
B10  
C9  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D9  
D8  
D7  
B12  
B11  
C12  
C11  
C10  
D12  
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.  
www.austriamicrosystems.com Revision 1.13  
185 - 194  
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