AS3525-A/-B C22O22
Data Sheet, Confidential
7.4
Audio and Power Management functions
7.4.1
SYSTEM
7.4.1.1 General
The system block handles the power up, power down and regulator voltage settings of the AFE.
7.4.1.2 Power Up
The chip powers up when on of the following condition is true:
•
•
•
•
High signal on the PWR_UP pin (>80ms, >1V & >1/3 BVDD)
Input voltage on the UVDD pin (USB plug in: >80ms, BVDD>1.5V, UVDD>4.5V)
Input voltage on the CHG_IN pin (charger plug in: >80ms, BVDD>1.5V, CHG_IN>4.0V)
Input voltage on BVDD pin (battery change: >1.35V)
To hold the chip in power up mode the PwrUpHld bit in the SYSTEM register (0x20h) is set.
7.4.1.3 Power Down
The chip automatically shuts off if one of the following conditions arises:
1. Clearing the PwrUpHld bit in SYSTEM register (0x20h)
2. I2C watchdog power down if enabled (no serial reading for >1s, has to be enabled)
3. BVDD drops below the minimum threshold voltage (<2.7V)
4. Junction temperature reaches maximum threshold, set in SUPERVISOR register (0x24h)
5. High signal on the PWR_UP pin for more than (>6s, >1V & >1/3 BVDD).
Figure 44 Power Up Timing
Power up from PwrUp, CHG_IN,
VBUS or RTCSUP pin
BVDD
rising with VBAT1 supply (DCDC3V)
VREF, IREF
rising with vdd_bandgap
QLDO1 & 2
AVDD & DVDD for internal supply
EN LDO2 + DCDC
QLDO2=ok
Enable CP Sequence
start sequencer with 1.2 MHz clock
+2ms
VREF=ok
Enable PVDD
Enable IOVDD
+4ms
start up with length regulator (200mA)
+6ms
Enable CVDD
+10ms
charge pump (50mA) enable unlock, enable
via I2C setting
PowerGood = XRES
+8ms
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