A67P16181/A67P06361 Series
SLEEP Mode
SLEEP Mode is a low current “Power-down” mode in which
the device is deselected and current is reduced to ISB2Z. This
duration of SLEEP Mode is dictated by the length of time the
ZZ is in a HIGH state. After entering SLEEP Mode, all inputs
except ZZ become disabled and all outputs go to High-Z.
The ZZ pin is asynchronous, active high input that causes
the device to enter SLEEP Mode. When the ZZ pin
becomes logic HIGH, ISB2Z is guaranteed after the time tZZI
is met. Any operation pending when entering SLEEP Mode
is not guaranteed to successfully complete. Therefore,
SLEEP Mode (READ or WRITE) must not be initiated until
valid pending operations are completed. Similarly, when
exiting SLEEP Mode during tRZZ, only a DESELECT or
READ cycle should be given while the SRAM is transitioning
out of SLEEP Mode.
SLEEP Mode Electrical Characteristics
(VCC, VCCQ = +2.5V±5%)
Symbol
ISB2Z
tZZ
Parameter
Conditions
Min.
Max.
TBD
Unit
mA
ns
Note
Current during SLEEP Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
ZZ ≥ VIH
-
0
0
-
2(tKHKH)
2(tKHKH)
2(tKHKH)
1
1
1
1
tRZZ
ns
tZZI
ns
tRZZI
0
ns
Note : 1. This parameter is sampled.
SLEEP Mode Waveform
CLK
tZZ
tRZZ
ZZ
tZZI
I
SUPPLY
IISB2Z
tRZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Output
(Q)
High-Z
: Don't Care
PRELIMINARY
(August, 2004, Version 0.1)
14
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
