A43E26161
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
µF
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
CDC1
CDC2
0.1 + 0.01
0.1 + 0.01
µF
Note: 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C or TA = -25ºC to +85ºC)
Speed
-95
Units Note
Symbol
Parameter
Test Conditions
Operating Current
(One Bank Active)
Burst Length = 1
40
Icc1
mA
mA
1
tRC ≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA
CKE ≤ VIL(max), tCC = 15ns
Icc2 P
0.3
0.5
Precharge Standby Current
in power-down mode
Icc2 PS
CKE ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC2N
5.5
Precharge Standby Current
in non power-down mode
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable.
ICC2NS
2
ICC3P
ICC3N
Active Standby current in
non power-down mode
(One Bank Active)
1.5
CKE ≤ VIL(max), tCC = 15ns
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
12
50
Operating Current
(Burst Mode)
IOL = 0mA, Page Burst
All bank Activated, tCCD = tCCD (min)
ICC4
ICC5
mA
mA
1
2
90
Refresh Current
tRC ≥ tRC (min)
TCSR Range
4 Banks
<45°C
200
<70°C
<85°C
600
350
TBD
TBD
TBD
TBD
50
ICC6
Self Refresh Current
CKE ≤ 0.2V
2 Banks
1 Banks
1/2 Bank
1/4 Bank
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
uA
uA
ICC7
Deep Power Down Current
CKE ≤ 0.2V
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).
2. Refresh period is 64ms. Addresses are changed only one time during tCC(min).
(December, 2004, Version 1.0)
5
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
