A43E26161
Pin Descriptions
Symbol
Name
Description
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA11, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
A0~A11
Address
BS0, BS1
Bank Select Address
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
RAS
CAS
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Column Address
Strobe
Write Enable
Enables write operation and Row precharge.
WE
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data Input/Output
Mask
L(U)DQM
DQ0-15
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
Power
Supply/Ground
VDD/VSS
Power Supply: +1.7V ~ 1.95V/Ground
Data Output
Power/Ground
VDDQ/VSSQ
NC/RFU
Provide isolated Power/Ground to DQs for improved noise immunity.
No Connection
(December, 2004, Version 1.0)
3
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
