A43E26161
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10
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12
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14
15
16
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CLOCK
CKE
* Note 4
* Note 2
t
RC
min.
t
SS
* Note 6
* Note 1
* Note 3
t
SS
* Note 5
CS
RAS
CAS
* Note 7
* Note 7
ADDR
BS0, BS1
A10/AP
WE
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Exit
Auto Refresh
Self Refresh Entry
: Don't care
* Note : TO ENTER SELF REFRESH MODE
1. and CKE should be low at the same clock cycle.
CS RAS CAS
,
&
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5.
starts from high.
CS
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.
If the system uses burst refresh.
(December, 2004, Version 1.0)
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AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
