欢迎访问ic37.com |
会员登录 免费注册
发布采购

A29002TL-70 参数 Datasheet PDF下载

A29002TL-70图片预览
型号: A29002TL-70
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×8位CMOS 5.0伏只,引导扇区闪存 [256K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory]
分类和应用: 闪存
文件页数/大小: 32 页 / 314 K
品牌: AMICC [ AMIC TECHNOLOGY ]
 浏览型号A29002TL-70的Datasheet PDF文件第9页浏览型号A29002TL-70的Datasheet PDF文件第10页浏览型号A29002TL-70的Datasheet PDF文件第11页浏览型号A29002TL-70的Datasheet PDF文件第12页浏览型号A29002TL-70的Datasheet PDF文件第14页浏览型号A29002TL-70的Datasheet PDF文件第15页浏览型号A29002TL-70的Datasheet PDF文件第16页浏览型号A29002TL-70的Datasheet PDF文件第17页  
A29002/A290021 Series  
bits are required for sector and mode information. Refer to  
Table 6 to compare outputs for I/O2 and I/O6.  
I/O6: Toggle Bit I  
Toggle Bit I on I/O6 indicates whether an Embedded  
Program or Erase algorithm is in progress or complete, or  
whether the device has entered the Erase Suspend mode.  
Toggle Bit I may be read at any address, and is valid after  
Figure 5 shows the toggle bit algorithm in flowchart form,  
and the section " I/O2: Toggle Bit II" explains the algorithm.  
See also the " I/O6: Toggle Bit I" subsection. Refer to the  
Toggle Bit Timings figure for the toggle bit timing diagram.  
The I/O2 vs. I/O6 figure shows the differences between I/O2  
and I/O6 in graphical form.  
the rising edge of the final  
sequence (prior to the program or erase operation), and  
during the sector erase time-out.  
During an Embedded Program or Erase algorithm  
operation, successive read cycles to any address cause  
pulse in the command  
WE  
Reading Toggle Bits I/O6, I/O2  
Refer to Figure 5 for the following discussion. Whenever  
the system initially begins reading toggle bit status, it must  
read I/O7 - I/O0 at least twice in a row to determine whether  
a toggle bit is toggling. Typically, a system would note and  
store the value of the toggle bit after the first read. After the  
second read, the system would compare the new value of  
the toggle bit with the first. If the toggle bit is not toggling,  
the device has completed the program or erase operation.  
The system can read array data on I/O7 - I/O0 on the  
following read cycle.  
I/O6 to toggle. (The system may use either  
control the read cycles.) When the operation is complete,  
I/O6 stops toggling.  
After an erase command sequence is written, if all sectors  
selected for erasing are protected, I/O6 toggles for  
approximately 100ms, then returns to reading array data. If  
not all selected sectors are protected, the Embedded  
Erase algorithm erases the unprotected sectors, and  
ignores the selected sectors that are protected.  
or  
to  
CE  
OE  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the system  
also should note whether the value of I/O5 is high (see the  
section on I/O5). If it is, the system should then determine  
again whether the toggle bit is toggling, since the toggle bit  
may have stopped toggling just as I/O5 went high. If the  
toggle bit is no longer toggling, the device has successfully  
completed the program or erase operation. If it is still  
toggling, the device did not complete the operation  
successfully, and the system must write the reset  
command to return to reading array data.  
The remaining scenario is that the system initially  
determines that the toggle bit is toggling and I/O5 has not  
gone high. The system may continue to monitor the toggle  
bit and I/O5 through successive read cycles, determining  
the status as described in the previous paragraph.  
Alternatively, it may choose to perform other system tasks.  
In this case, the system must start at the beginning of the  
algorithm when it returns to determine the status of the  
operation (top of Figure 5).  
The system can use I/O6 and I/O2 together to determine  
whether a sector is actively erasing or is erase-suspended.  
When the device is actively erasing (that is, the Embedded  
Erase algorithm is in progress), I/O6 toggles. When the  
device enters the Erase Suspend mode, I/O6 stops  
toggling. However, the system must also use I/O2 to  
determine which sectors are erasing or erase-suspended.  
Alternatively, the system can use I/O7 (see the subsection  
on " I/O7 :  
Polling").  
Data  
If a program address falls within a protected sector, I/O6  
toggles for approximately 2ms after the program command  
sequence is written, then returns to reading array data.  
I/O6 also toggles during the erase-suspend-program mode,  
and stops toggling once the Embedded Program algorithm  
is complete.  
The Write Operation Status table shows the outputs for  
Toggle Bit I on I/O6. Refer to Figure 5 for the toggle bit  
algorithm, and to the Toggle Bit Timings figure in the "AC  
Characteristics" section for the timing diagram. The I/O2 vs.  
I/O6 figure shows the differences between I/O2 and I/O6 in  
graphical form. See also the subsection on " I/O2: Toggle  
Bit II".  
I/O5: Exceeded Timing Limits  
I/O5 indicates whether the program or erase time has  
exceeded a specified internal pulse count limit. Under  
these conditions I/O5 produces a "1." This is a failure  
condition that indicates the program or erase cycle was not  
successfully completed.  
The I/O5 failure condition may appear if the system tries to  
program a "1 "to a location that is previously programmed  
to "0." Only an erase operation can change a "0" back to a  
"1." Under this condition, the device halts the operation,  
and when the operation has exceeded the timing limits,  
I/O5 produces a "1."  
I/O2: Toggle Bit II  
The "Toggle Bit II" on I/O2, when used with I/O6, indicates  
whether a particular sector is actively erasing (that is, the  
Embedded Erase algorithm is in progress), or whether that  
sector is erase-suspended. Toggle Bit II is valid after the  
rising edge of the final  
sequence.  
I/O2 toggles when the system reads at addresses within  
pulse in the command  
WE  
those sectors that have been selected for erasure. (The  
Under both these conditions, the system must issue the  
reset command to return the device to reading array data.  
system may use either  
or  
to control the read  
CE  
OE  
cycles.) But I/O2 cannot distinguish whether the sector is  
actively erasing or is erase-suspended. I/O6, by  
comparison, indicates whether the device is actively  
erasing, or is in Erase Suspend, but cannot distinguish  
which sectors are selected for erasure. Thus, both status  
(February, 2002, Version 1.0)  
13  
AMIC Technology, Inc.  
 复制成功!