A25LQ080 Series
Read Status Register (RDSR)
Program, Dual Input Fast Program, Quad Input Fast Program,
Sector Erase, Block Erase, Chip Erase, and Write Status
Register.
The Read Status Register (RDSR) instruction allows the
Status Register to be read. The instruction code of “05h” is
for Status Register-1 and “35h” is for Status Register-2. The
Status Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended
to check the Write In Progress (WIP) bit before sending a
new instruction to the device. It is also possible to read the
Status Register continuously, as shown in Figure 5.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, and BP0)
bits are non-volatile read/write bits in the status register (b4,
b3, and b2) that provide Write Protection control and status.
Block Protect bits can be set using the Write Status Register
Instruction (see tW in AC characteristics). All, none or a
portion of the memory array can be protected from Program
and Erase instructions (see Table 1. Protected Area Sizes).
These bits can be set with the Write Status Register
Instruction depending on the state of SRP0 and WEL bit. The
factory default setting for the Block Protect Bits is 0 which
means none of the array protected. For value of BP2, BP1,
BP0 after power-on, see note please.
Table 4-a Status Register-1 Format
b7
b6
b5
b4
b3
b2
b1
b0
SRP0 SEC TB BP2 BP1 BP0 WEL WIP
Status Register Protect 0
(Non-volatile)
Sector Protect
(Non-volatile)
TB bit. The non-volatile Top/Bottom (TB) bit controls if the
Block Protect Bits (BP2, BP1, BP0) protect from the Top
(TB=0) or the Bottom (TB=1) of the array as shown in Table 1.
Protected Area Sizes. The factory default setting is TB=0.
The TB bit can be set with the Write Status Register
Instruction depending on the state of SRP0 and WEL bit.
Top/Bottom Bit
(Non-volatile)
Block Protect Bits
(Non-volatile)
Write Enable Latch Bit
Write In Progress Bit
SEC bit. The non-volatile Sector Protect (SEC) bit in the
status register (b6) controls if the Block Protect Bits (BP2,
BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks
(SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array
as shown in Table 1. Protected Area Sizes. This bit can be
set with the Write Status Register Instruction depending on
the state of the SRP0, and WEL bit. The factory default
setting for SEC is 0.
Table 4-b Status Register-2 Format
b15
SUS CMP
b14
b13 b12 b11 b10
b9
b8
0
0
0
0
APT QE
Suspend Status
(Volatile)
SRP0 bit. The Status Register Protect bit (SRP0) is a
non-volatile read/write bit in the status register (b7). The
SRP0 bit controls the method of write protection: software
protection, hardware protection, or one time programmable
protection.
Complement Protect
(Non-volatile)
Reserved
All Protect
(Auto Write Protect)
Quad Enable
(Non-volatile)
QE bit. The Quad Enable (QE) bit is a non-volatile read/write
bit in the status register (b9) that allows Quad SPI operation.
Reserved
When QE is set to 0(factory default), the
pin and
W
The status and control bits of the Status Register are as
follows:
pin are enabled. When QE is set to 1, the
pin
W
HOLD
and
pin become IO2 and IO3. This bit can be set with
HOLD
WIP bit. The Write In Progress (WIP) bit is a read only bit in
the status register (b0) that is set to a 1 state when the
device is busy with a Write Status Register, Program or
Erase cycle. During this time the device will ignore further
instructions except for the Read Status Register, Suspend
and Resume instructions (see tW, tPP, tSE, tBE, and tCE in AC
Characteristics). When the program, erase, write status
register instruction has completed or Program/Erase
Suspend instruction is executed, the WIP bit will be cleared
to a 0 state indicating the device is ready for further
instructions.
the Write Status Register Instruction depending on the state
of the SRP0 and WEL bit. The factory default setting for QE
is 0.
APT bit. The All Protect (APT) bit is a non-volatile read/write
bit in the status register (b10). Whole chip will be kept in
write-protect state after power-on if this bit is set to 1. This bit
can be set with the Write Status Register Instruction
depending on the state of SRP0 and WEL bit. The factory
default setting for APT is 0.
CMP bit. The Complement Protect (CMP) bit is a non-volatile
read/write bit in the status register (b14). It’s used in
conjunction with SEC, TB, BP2, BP1, BP0 bits to provide
more flexibility for the array protection. Once CMP is set to 1,
previous array protection set by SEC, TB, BP2, BP1 and BP0
will be reversed. Please refer to table 1 for more details. The
factory default setting for CMP is 0.
WEL bit. The Write Enable Latch (WEL) bit is a read only bit
in the status register (b1) that is set to a 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to a 0
when the device is write disabled or Program/Erase
suspended. A write disable state occurs upon power-up or
after any of the following instructions: Write Disable, Page
(April, 2016, Version 1.0)
14
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
