FS612509-01/-02
1:9 Zero-Delay Clock Buffer IC
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
11
14
3
4
5
8
9
21
20
17
16
23
1
24
13
12
6, 7, 18, 19
2, 10, 15, 22
TYPE
DI
DI
DO
DO
DO
DO
DO
DO
DO
DO
DO
P
P
DI
DI
DO
P
P
NAME
1G
2G
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
AVDD
AGND
CLK
FBIN
FBOUT
GND
VDD
DESCRIPTION
Output enable stops Bank 1 clocks (1Y0 – 1Y4) in a low state when this pin is low
Output enable stops Bank 2 clocks (2Y0 – 2Y3) in a low state when this pin is low
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output
Power Supply / Test mode enable. This pin provides the power supply to the internal PLL. When the
pin is pulled low, the PLL is bypassed and the output clocks directly follow the input clock
PLL supply ground
Reference clock input (Note:
-02 version has a pull-down on this pin)
Feedback clock input, connected to FBOUT to complete the loop
Feedback output clock
Ground for all clock outputs
Power supply for all clock outputs
Bank 2
Enabled by 2G
Bank 1
Enabled by 1G
ISO9001
QS9000
2
AMI [ AMI SEMICONDUCTOR ]
