AMIS-721250: Contact Image Sensor
7.0 Absolute Maximum Ratings
Table 4: Absolute Maximum Ratings
Parameter
Power supply voltage (Vdd)
Clock input voltage high level
Clock input voltage low level
Operating temperature
Operating humidity
Storage temperature
Storage humidity
Note:
1.
Applies to all clocks; GBST, SI and CLK.
(1)
(1)
Data Sheet
Max.
8
Vdd + 0.5
-0.5
-10 to +50
+10 to +85
-25 to +75
+10 to +90
Units
V
V
V
°C
RH%
°C
RH%
8.0 Timing Requirements
Table 5: Timing Requirements
Parameter
Clock (CLK) period
Clock (CLK) pulse width
Clock (CLK) duty cycle
(1)
Data setup time
Data hold time
(1)
(2)
Symbol
CLKp
CLKpw
Tset
Thold
CLKrt
CLKft
Min.
666
Typ.
800
400
50
Max.
4000
20
25
70
70
50
50
70
70
100
30
Units
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock (CLK) rise time
Clock (CLK) fall time
(2)
(2)
End of scan (SO) rise time
End of scan (SO) fall time
SOrt
SOft
(3)
(2)
Global start (GBST) rise time
Global start (GBST) fall time
Pixel rise time
Pixel fall time
Notes:
1.
2.
3.
4.
5.
(4,5)
GBSTrt
GBSTft
Prt
Pft
(3)
(4,5)
The shift register will load on all falling CLK edges, so setup and hold times (Tset, Thold) are needed to prevent the loading of multiple start pulses. This would
occur if the GBST remains high during two fallings edges of the CLK signal. See Figure 7.
SI starts the register scanning and the first active pixel is read out on the 56
th
clock of the CLK signal. However, when multiple sensors are sequentially scanned,
as in CIS modules, the SO from the predecessor sensor becomes the SI to the subsequent sensor, hence the SI clock = the SO clock.
As discussed under the third unique feature, the GBST starts the initialization process and preprocesses all sensors simultaneously in the first 55 clock cycles (110
pixels) before the first pixel is scanned onto the video line from the first sensor.
The transition between pixels does not always reach the dark offset level as shown in the timing diagrams, see Vout. The timing diagrams show the transition
doing so for illustration purposes; however a stable pixel sampling point does exist for every pixel.
The pixel rise time is defined as the time from when the CLK’s rising edge has reached 50 percent of its maximum amplitude to the point when a pixel has reached
90 percent of its maximum amplitude. The pixel fall time is defined as the time from when a pixel’s charge begins to decrease from its maximum amplitude to
within 10 percent of the lowest point before the next pixel begins to rise.
Figures 4 and 5 show the initialization of the first sensor in relation to its subsequent cascaded sensors. The SIC selects the first sensor
to operate with 55 clock cycles of delay by connecting it to Vdd on the first sensor and to ground for all of the subsequent sensors.
Hence the first sensor will operate with 110 inactive pixels being clocked out before its first active pixel is clocked out.
AMI Semiconductor
– Dec. 05, M-20496-004
www.amis.com
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