P R E L I M I N A R Y
SRAM CHARACTERISTICS
Write Cycle
Speed
Parameter
Description
Symbol
Unit
70
70
60
85
85
70
tWC
tCw
tAS
Write Cycle Time
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address Setup Time
0
tAW
tBW
tWP
tWR
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
Min
Min
Min
Min
Min
Max
Min
Min
Min
60
60
50
70
70
60
Write Recovery Time
0
0
tWHZ
Write to Output High-Z
ns
20
30
25
35
tDW
tDH
tOW
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
ns
ns
ns
0
5
tWC
Address
CS1#s
tCW
(See Note 2)
tWR (See Note 3)
tAW
CS2s
tCW
(See Note 2)
tBW
UB#s, LB#s
tWP
(See Note 5)
WE#
tAS
(See Note 4)
tDH
tDW
(See Note 9)
(See Note 6)
(See Note 9)
High-Z
Data In
High-Z
Data Valid
tWHZ
tOW
Data Out
(See Note 7)
Notes:
1. WE# controlled.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
6. If CE1# goes low (or CE2 goes high) at the same time or after WE# goes low, the outputs will remain at high impedance.
7. If CE1# goes high (or CE2 goes low) at the same time or before WE# goes high, the outputs will remain at high impedance.
8. If OE# is high during the write cycle, the outputs will remain at high impedance.
9. Output data may be present on the bus at this time; input signals should not be applied.
Figure 30. SRAM Write Cycle—WE# Control
54
Am42DL6404G
March 20, 2002
AMD [ AMD ]
