P R E L I M I N A R Y
SRAM CHARACTERISTICS
Read Cycle
Speed
Parameter
Description
Symbol
Unit
70
70
70
70
35
70
85
85
85
85
45
85
tRC
tAA
tCO1, tCO2
tOE
Read Cycle Time
Min
ns
ns
ns
ns
ns
Address Access Time
Chip Enable to Output
Output Enable Access Time
LB#s, UB#s to Access Time
Max
Max
Max
Max
tBA
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
t
LZ1, tLZ2
Min
10
ns
tBLZ
tOLZ
tHZ1, tHZ2
tBHZ
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Min
Min
10
5
ns
ns
ns
ns
ns
ns
Max
Max
Max
Min
25
25
25
10
UB#s, LB#s Disable to High-Z Output
Output Disable to High-Z Output
Output Data Hold from Address Change
tOHZ
tOH
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
Figure 28. SRAM Read Cycle—Address Controlled
52
Am42DL6404G
March 20, 2002
AMD [ AMD ]
