P R E L I M I N A R Y
Table 1.
Operation
(Notes 1, 2)
Read from Flash
Device Bus Operations—Flash Word Mode, CIOf = V
IH
; SRAM Word Mode, CIOs = V
CC
CE#f CE1#s CE2s OE# WE#
L
H
X
H
X
H
X
L
H
X
H
X
L
X
L
X
L
H
X
L
X
L
X
L
X
L
H
L
X
H
L
X
L
H
SA
X
Addr.
A
IN
A
IN
X
X
X
X
SADD,
A6 = L,
A1 = H,
A0 = L
SADD,
A6 = H,
A1 = H,
A0 = L
X
LB#s UB#s RESET#
X
X
H
WP#/ACC DQ7–
(Note 4)
DQ0
D
OUT
D
IN
High-Z
DQ15–
DQ8
D
OUT
D
IN
High-Z
Write to Flash
L
V
CC
±
0.3 V
L
H
L
X
X
X
H
V
CC
±
0.3 V
H
(Note 4)
Standby
X
H
H
X
X
H
H
X
X
X
X
X
X
L
X
X
X
X
L
X
H
Output Disable
Flash Hardware
Reset
Sector Protect
(Note 5)
L/H
High-Z
High-Z
X
L
L/H
High-Z
High-Z
L
X
H
X
X
V
ID
L/H
D
IN
X
Sector Unprotect
(Note 5)
Temporary Sector
Unprotect
L
X
H
X
X
X
V
ID
(Note 6)
D
IN
X
X
X
X
X
X
L
X
L
L
H
L
L
H
V
ID
(Note 6)
D
IN
D
OUT
High-Z
D
OUT
D
OUT
High-Z
D
IN
D
IN
High-Z
Read from SRAM
H
L
H
L
H
X
A
IN
H
L
L
H
X
High-Z
D
OUT
D
IN
Write to SRAM
H
L
H
X
L
X
A
IN
H
L
H
X
High-Z
D
IN
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5 V, V
HH
= 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = V
IL
, CE1#s = V
IL
and CE2s = V
IH
at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V
IL
, the boot sectors will be protected. If WP#/ACC = V
IH
the boot sectors protection will be removed.
If WP#/ACC = V
ACC
(9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
6. If WP#/ACC = V
IL
, the two outermost boot sectors remain protected. If WP#/ACC = V
IH
, the two outermost boot sector protection
Unprotection”. If WP#/ACC = V
HH,
all sectors will be unprotected.
September 5, 2002
Am41DL32x8G
11
AMD [ ADVANCED MICRO DEVICES ]
