P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
Parameter
Speed Options
Unit
JEDEC
tAVAV
Std
tWC
tAS
Description
70
85
Write Cycle Time (Note 1)
Address Setup Time (WE# to Address)
Min
Min
70
85
ns
ns
tAVWL
0
15
45
0
Address Setup Time to CE#f Low During Toggle
Bit Polling
tASO
tAH
Min
Min
Min
ns
ns
ns
tELAX
Address Hold Time
Address Hold time from CE#f or OE# High During
Toggle Bit Polling
tAHT
tDVEH
tEHDX
tDS
tDH
Data Setup Time
Data Hold Time
Min
Min
35
45
ns
ns
0
0
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
CE#f Pulse Width
CE#f Pulse Width High
30
35
tCPH
30
5
Byte
Programming Operation
(Note 2)
tWHWH1
tWHWH1
µs
Word
7
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
Notes:
tWHWH1
tWHWH2
Typ
Typ
4
µs
Sector Erase Operation (Note 2)
0.4
sec
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
54
Am41DL32x8G
September 5, 2002
AMD [ AMD ]
