Notes:
1. The ROMCSx address decode is programmable for an early decode (via bit 5 in CSC index 23h, 25h, and 27h). The early
address-decode is available to provide the ROMCSx by qualifying the address signals only; it is not qualified with the com-
mands (ROMRD, ROMWR). The timing parameter t2a pertains to the early address-decode feature being enabled (ROMCSx
is address-decode only). Parameters t2b and t2c are observed when the early address-decode feature is disabled (ROMCSx
is address-decode qualified with command). The early decode can be enabled for both Fast-mode and Normal-mode ROM
accesses.
2. When a x32 DRAM or VL bus is enabled, additional delay must be added to accommodate for the delay through the external
data buffers required for the SD bus in this mode.
3. There are two types of programmable wait states. The first programmable wait state is always used in the first access for
either burst or non-burst supported device. It starts at the assertion of the chip select or at the transition of SA3–SA0, which-
ever occurs later. The second programmable wait state is used only for any subsequent burst read accesses to a burst mode
ROM device. It starts at the transition of SA3–SA0. The burst address valid duration depends on which wait state is used. If
the wait state is set to zero, then the minimum address duration is 30 ns (one bus clock cycle).
4. If wait states are added via the deassertion of IOCHRDY, the data setup time to IOCHRDY assertion is 0 ns (minimum).
t2b
SA25–SA4
t1
t1
t4
t6
SA3–SA0
t7
ROMCSx
ROMWR
t28
t6
t25
t27
t8
t9
ROMRD
SD15–SD0
D15–D0
(x32 ROM)
DBUFOE
R32BFOE
DBUFRDH
DBUFRDL
Figure 25. Fast Mode 8-/16-/32-Bit ROM/Flash Memory Read Cycle
94
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
