t2b
SA25–SA4
SA3–SA0
t6
t1
t4
t10
1
t1
0
2
t2a
ROMCSx
ROMWR
3 * t9
ROMRD
SD7–SD0
Notes:
The ROM controller fetches the number of bytes requested by the CPU as dictated by the CPU BE (Byte Enable) signals and
returns the data as a single transfer. In this example, BE was set to “0001”. Therefore, the ROM controller generates additional
addresses to read all three bytes before returning them to the CPU.
Figure 26. Fast Mode CPU Read of Three Consecutive Bytes from 8-Bit ROM/Flash Memory
t2b
t14
SA25–SA0
ROMCSx
t2a
t5
t13
t29
t26
t27
t8
t11
t12
ROMWR
ROMRD
SD15–SD0
D15–D0
(x32 ROM)
DBUFOE
R32BFOE
DBUFRDL
DBUFRDH
Figure 27. Fast Mode 8-/16-/32-Bit Flash Memory Write Cycles
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
95
AMD [ AMD ]
