Table 36. ROM/Flash Memory Cycles
33-MHz
External Bus
Symbol
Parameter Description
Notes
Unit
Min
Max
6
t1
SA3–SA0 delay from SA31–SA4
SA stable to ROMCSx assertion
ns
ns
ns
1
1
t2a
t2b
6
SA stable to ROMCSx assertion
20
when qualified with command (ROMRD or ROMWR)
1
t2c
SA stable to ROMCSx assertion
100
ns
when qualified with command (ROMRD or ROMWR)
1
2
t3
t4
ROMCSx deassertion to SA change
53
15
ns
ns
SD setup to ROMRD or ROMCSx deassertion or burst address
switching, whichever is first, for 8-/16-/32-bit device
t5
t6
ROMWR setup to ROMCSx
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
3
Data hold from SA, ROMRD, or ROMCSx change, whichever is first
ROMCSx pulse width
t7
25
t8
DBUFOE, R32BFOE setup to ROMRD, ROMWR Low
ROMRD pulse width
-8
3
3
3
2
2
2
t9
25
25
25
t10
t11
SA3–SA0 burst address valid duration
ROMWR pulse width
t12
t13
t14
t15
t16a
t16b
t17a
t17b
t18
t19
t20
t21a
t21b
t22
t23
t24a
t24b
t25
t26
t27
t28
t29
SD setup to ROMWR assertion for 32-bit device
SD hold from ROMWR deassertion
17
20
20
SA hold from ROMWR deassertion
ROMRD delay from SA stable
115
530
240
ROMRD, ROMWR pulse width for 8-bit device
ROMRD, ROMWR pulse width for 16-bit device
Data setup from ROMRD for 8-bit device
Data setup from ROMRD for 16-bit device
ROMRD deassertion to SA unstable
2, 4
2, 4
489
209
20
0
2
Data hold from ROMRD deassertion
SA hold from ROMWR deassertion
53
-29
33
26
125
2
2
2
SD setup to ROMWR assertion for 16-bit device
SD setup to ROMWR assertion for 8-bit device
SD hold from ROMWR deassertion
IOCHRDY assertion to ROMRD, ROMWR deassertion
IOCHRDY deassertion from ROMRD, ROMWR for 8-bit
IOCHRDY deassertion from ROMRD, ROMWR for 16-bit
R32BFOE/DBUFOE hold from ROMRD High
R32BFOE/DBUFOE hold from ROMWR High
DBUFRDL, DBUFRDH setup to ROMRD, ROMWR Low
DBUFRDL, DBUFRDH hold from ROMRD High
DBUFRDL, DBUFRDH hold from ROMWR high
378
66
0
26
-8
0
26
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
93
AMD [ AMD ]
