Table 7. Pin State Table—Memory Interface1
Signal Name
[Alternate
Function]
Max
Load Supply
(pF)
Power
Down Note 5 V
Group
Pin
#
Output
Drive
Reset
State Operation
Normal
Suspend
State
Type
2
CASH0
CASH1
CASL0
CASL1
D0
D13
A17
B15
C14
B10
A10
C9
B9
O
O
O
O
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
D
30
30
30
30
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
250
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
H
O
O[L][TS-PD]
O[L][TS-PD]
O[L][TS-PD]
O[L][TS-PD]
TS-PD
A
2
D
H
O
A
2
D
H
O
A
2
D
H
O
A
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
D
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
I-PU
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
B-PD
D1
TS-PD
D2
TS-PD
D3
TS-PD
D4
A9
TS-PD
D5
B8
TS-PD
D6
C8
A7
TS-PD
D7
TS-PD
D8
B7
TS-PD
D9
A6
TS-PD
D10
D11
D12
D13
D14
D15
C7
B6
TS-PD
TS-PD
A5
TS-PD
C6
B5
TS-PD
TS-PD
A4
TS-PD
KBD_ROW0
[CASL2]
B19 STI-OD
[O]
IOD-PU
O
I-PU
O[L][TS-PD]
A
2
KBD_ROW1
[CASL3]
D16 STI-OD
[O]
D
D
250
250
250
250
250
250
VCC
VCC
VCC
VCC
VCC
VCC
I-PU
I-PU
I-PU
I-PU
I-PU
I-PU
IOD-PU
O
I-PU
O[L][TS-PD]
A
2
KBD_ROW2
[CASH2]
C17 STI-OD
[O]
IOD-PU
O
I-PU
O[L][TS-PD]
A
2
KBD_ROW3
[CASH3]
B18 STI-OD
[O]
D
IOD-PU
O
I-PU
O[L][TS-PD]
A
2
KBD_ROW4
[RAS2]
D15 STI-OD
[O]
C–E3
C–E3
C–E3
IOD-PU
O
I-PU
O[L][TS-PD]
A
2
KBD_ROW5
[RAS3]
C16 STI-OD
[O]
IOD-PU
O
I-PU
O[L][TS-PD]
A
5
KBD_ROW6
[MA12]
B17 STI-OD
[O]
IOD-PU
O
I-PU
TS-PD
6
6
MA0 {CFG0}
MA1 {CFG1}
MA2 {CFG2}
MA3 {CFG3}
MA4
C10
B11
A12
B12
C11
A14
B13
C12
A15
B14
O {I}
O {I}
O {I}
O {I}
O
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
C–E3
70
70
70
70
70
70
70
70
70
70
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
I-PD
I-PD
I-PD
I-PD
I-PD
L
O
O
O
O
O
O
O
O
O
O
TS-PPD
TS-PPD
TS-PPD
TS-PPD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
TS-PD
6, 7
6
6, 8
8
MA5
O
8
MA6
O
L
8
MA7
O
L
8
MA8
O
L
8
MA9
O
L
44
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
