Control and Status Registers (Continued)
RAP
Default Value
Addr
Symbol
CSR71
CSR72
CSR73
CSR74
CSR75
CSR76
CSR77
CSR78
CSR79
CSR80
CSR81
CSR82
CSR83
CSR84
CSR85
CSR86
CSR87
CSR88
CSR89
CSR90
CSR91
CSR92
CSR93
CSR94
CSR95
CSR96
CSR97
CSR98
CSR99
CSR100
CSR101
CSR102
CSR103
CSR104
CSR105
CSR106
CSR107
After H_RESET
Comments
Use
T
71
72
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu 1410
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
262 5003
Reserved
RCVRC: RCV Ring Counter
Reserved
73
74
XMTRC: XMT Ring Counter
Reserved
T
75
76
RCVRL: RCV Ring Length
Reserved
S
77
78
XMTRL: XMT Ring Length
Reserved
S
79
80
DMATCFW: DMA Transfer Counter and FIFO Threshold
S
81
Reserved
82
Transmit Descriptor Pointer Address Lower
Reserved
S
83
84
DMABA: Address Register Lower
DMABA: Address Register Upper
DMABC: Buffer Byte Counter
Reserved
T
T
T
85
86
87
88
Chip ID Register Lower
Chip ID Register Upper
Reserved
T
T
89
uuuu 262
90
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu 0200
uuuu uuuu
uuuu uuuu
uuuu 0105
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
91
Reserved
T
T
92
RCON: Ring Length Conversion
Reserved
93
94
Reserved
95
Reserved
96
Reserved
97
Reserved
98
Reserved
99
Reserved
100
101
102
103
104
105
106
107
Bus Timeout
S
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
210
Am79C978
AMD [ AMD ]
