Control and Status Registers (Continued)
RAP
Default Value
Addr
Symbol
CSR34
CSR35
CSR36
CSR37
CSR38
CSR39
CSR40
CSR41
CSR42
CSR43
CSR44
CSR45
CSR46
CSR47
CSR48
CSR49
CSR50
CSR51
CSR52
CSR53
CSR54
CSR55
CSR56
CSR57
After H_RESET
Comments
CXDAL: Current XMT Descriptor Address Lower
CXDAU: Current XMT Descriptor Address Upper
NNRDAL: Next Next Receive Descriptor Address Lower
NNRDAU: Next Next Receive Descriptor Address Upper
NNXDAL: Next Next Transmit Descriptor Address Lower
NNXDAU: Next Next Transmit Descriptor Address Upper
CRBC: Current Receive Byte Count
CRST: Current Receive Status
CXBC: Current Transmit Byte
CXST: Current Transmit Status
NRBC: Next RCV Byte Count
NRST: Next RCV Status
Use
T
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
T
T
T
T
T
T
T
T
T
T
T
POLL: Poll Time Counter
PI: Polling Interval
T
S
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
see register
description
58
CSR58
SWS: Software Style
S
59
60
61
62
63
64
65
66
67
68
69
70
CSR59
CSR60
CSR61
CSR62
CSR63
CSR64
CSR65
CSR66
CSR67
CSR68
CSR69
CSR70
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Reserved
T
T
T
T
T
T
T
T
T
PXDAL: Previous XMT Descriptor Address Lower
PXDAU: Previous XMT Descriptor Address Upper
PXBC: Previous Transmit Byte Count
PXST: Previous Transmit Status
NXBAL: Next XMT Buffer Address Lower
NXBAU: Next XMT Buffer Address Upper
NXBC: Next Transmit Byte Count
NXST: Next Transmit Status
Reserved
Reserved
Reserved
Am79C978
209
AMD [ AMD ]
