REGISTER SUMMARY
PCI Configuration Registers
Table 88. PCI Configuration Registers
Width
Access
Mode
Default
Value
Offset
Name
in Bit
16
16
16
16
8
00h
02h
PCI Vendor ID
PCI Device ID
PCI Command
PCI Status
RO
RO
RW
RW
RO
RO
RO
RO
RO
RW
RO
RO
RW
RW
RO
RO
RO
RW
RO
RO
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
1022h
2001h
0000h
0290h
50h
04h
06h
08h
PCI Revision ID
PCI Programming IF
PCI Sub-Class
PCI Base-Class
Reserved
09h
8
00h
0Ah
8
00h
0Bh
8
02h
0Ch
8
00h
0Dh
PCI Latency Timer
PCI Header Type
Reserved
8
00h
0Eh
8
00h
0Fh
8
00h
10h
PCI I/O Base Address
32
32
8
0000 0001h
0000 0000h
00h
14h
PCI Memory Mapped I/O Base Address
Reserved
18h - 2Bh
2Ch
PCI Subsystem Vendor ID
PCI Subsystem ID
16
16
32
8
00h
2Eh
00h
30h
PCI Expansion ROM Base Address
Capabilities Pointer
0000 0000h
40h
34h
31h - 3Bh
3Ch
Reserved
8
00h
PCI Interrupt Line
8
00h
3Dh
PCI Interrupt Pin
8
01h
3Eh
PCI MIN_GNT
8
06h
3Fh
PCI MAX_LAT
8
FFh
40h
PCI Capability Identifier
PCI Next Item Pointer
PCI Power Management Capabilities
PCI Power Management Control/Status
PCI PMCSR Bridge Support Extensions
PCI Data
8
01h
41h
8
00h
42h
16
16
8
00h
44h
00h
46h
00h
47h
8
00h
48h - FFh
Reserved
8
00h
Note: RO = read only, RW = read/write
Am79C978
207
AMD [ AMD ]
