Control and Status Registers
Table 89. Control and Status Registers (CSRs)
RAP
Addr
Symbol
CSR0
CSR1
CSR2
CSR3
CSR4
CSR5
CSR6
CSR7
CSR8
CSR9
CSR10
CSR11
CSR12
CSR13
CSR14
Default Value
uuuu 0004
uuuu uuuu
uuuu uuuu
uuuu 0000
uuuu 0115
uuuu 0000
uuuu uuuu
0uuu 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Comments
Am79C978 Controller Status Register
Use
R
S
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
Lower IADR: maps to location 16
Upper IADR: maps to location 17
S
Interrupt Masks and Deferral Control
S
Test and Features Control
R
R
S
Extended Control and Interrupt 1
RXTX: RX/TX Encoded Ring Lengths
Extended Control and Interrupt 1
R
S
LADRF0: Logical Address Filter — LADRF[15:0]
LADRF1: Logical Address Filter — LADRF[31:16]
LADRF2: Logical Address Filter — LADRF[47:32]
LADRF3: Logical Address Filter — LADRF[63:48]
PADR0: Physical Address Register — PADR[15:0][
PADR1: Physical Address Register — PADR[31:16]
PADR2: Physical Address Register — PADR[47:32]
S
S
S
S
S
S
see register
description
15
CSR15
MODE: Mode Register
S
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
CSR16
CSR17
CSR18
CSR22
CSR20
CSR21
CSR22
CSR23
CSR24
CSR25
CSR26
CSR27
CSR28
CSR29
CSR30
CSR31
CSR32
CSR33
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
IADRL: Base Address of INIT Block Lower (Copy)
IADRH: Base Address of INIT Block Upper (Copy)
CRBAL: Current RCV Buffer Address Lower
CRBAU: Current RCV Buffer Address Upper
CXBAL: Current XMT Buffer Address Lower
CXBAU: Current XMT Buffer Address Upper
NRBAL: Next RCV Buffer Address Lower
NRBAU: Next RCV Buffer Address Upper
BADRL: Base Address of RCV Ring Lower
BADRU: Base Address of RCV Ring Upper
NRDAL: Next RCV Descriptor Address Lower
NRDAU: Next RCV Descriptor Address Upper
CRDAL: Current RCV Descriptor Address Lower
CRDAU: Current RCV Descriptor Address Upper
BADXL: Base Address of XMT Ring Lower
BADXU: Base Address of XMT Ring Upper
NXDAL: Next XMT Descriptor Address Lower
NXDAU: Next XMT Descriptor Address Upper
T
T
T
T
T
T
T
T
S
S
T
T
T
T
S
S
T
T
Note:
u = undefined value, R = Running register, S = Setup register, T = Test register; all default values are in hexadecimal format.
208
Am79C978
AMD [ AMD ]
