against inadvertent writes (refer to Table 8 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
START
spurious system level signals during V power-up and
power-down transitions, or from system noise.
CC
RESET# = V
(Note 1)
ID
Low V
Write Inhibit
CC
When V
is less than V
, the device does not ac-
CC
LKO
Perform Erase or
Program Operations
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
RESET# = V
IH
CC
is greater than V
. The system must provide the
LKO
proper signals to the control pins to prevent uninten-
tional writes when V is greater than V
.
CC
LKO
Temporary Sector
Unprotect Completed
(Note 2)
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Notes:
Write cycles are inhibited by holding any one of OE#
1. All protected sectors unprotected.
= V , CE# = V or WE# = V . To initiate a write cy-
IL
IH
IH
2. All previously protected sectors are protected once
again.
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
Figure 2. Temporary Sector Unprotect Operation
If WE# = CE# = V and OE# = V during power
IL
IH
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
18
Am29LV017D
AMD [ AMD ]
