on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
Characteristics table represents the automatic sleep
mode current specification.
in the DC
CC4
I
in the DC Characteristics table represents the ac-
CC2
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RE-
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
SET# pin is driven low for at least a period of t , the
RP
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
CC
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V ±0.3 V, the device
SS
draws CMOS standby current (I
). If RESET# is held
CC4
at V but not within V ±0.3 V, the standby current will
IL
SS
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
V .) If CE# and RESET# are held at V , but not within
IH
IH
V
CC ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (t ) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
CE
time of t
(during Embedded Algorithms). The
READY
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, “RE-
SET#: Hardware Reset Pin”.
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
(not during Embedded Algo-
READY
after the RE-
RH
SET# pin returns to V .
IH
I
in the DC Characteristics table represents the
CC3
standby current specification.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Automatic Sleep Mode
Output Disable Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
When the OE# input is at V , output from the device is
IH
this mode when addresses remain stable for t
+ 30
disabled. The output pins are placed in the high imped-
ance state.
ACC
ns. The automatic sleep mode is independent of the
14
Am29LV017D
AMD [ AMD ]
