DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV017D Device Bus Operations
Operation
CE#
L
OE#
L
WE#
H
RESET#
Addresses
DQ0–DQ7
Read
Write
H
H
A
A
D
OUT
IN
IN
L
H
L
D
IN
V
0.3 V
±
V
0.3 V
±
CC
CC
Standby
X
X
X
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z
High-Z
X
Sector Addresses,
A6 = L, A1 = H, A0 = L
Sector Protect (See Note)
L
H
L
V
D
D
, D
, D
ID
IN
IN
OUT
OUT
Sector Addresses
A6 = H, A1 = H, A0 = L
Sector Unprotect (See Note)
L
H
X
L
V
V
ID
ID
Temporary Sector Unprotect
X
X
A
D
IN
IN
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 ± ±0.5 V, X = Don’t Care, A = Address In, D = Data In, D
= Data Out
IL
IH
ID
IN
IN
OUT
Note: The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
drive the CE# and OE# pins to V . CE# is the power
IL
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
CE# to V , and OE# to V .
IL
IH
remain at V .
IH
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “” section has details on erasing a sector
or the entire chip, or suspending/resuming the erase
operation.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I
in
CC1
the DC Characteristics table represents the active cur-
rent specification for reading array data.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
Am29LV017D
13
AMD [ AMD ]
