EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence
(see below)
Data Polling or Toggle Bit I
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
(Address/Command):
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional
Sector Address/30H
18805C-7
To insure the command has been accepted, the system software should check the status of DQ3 prior to and following
each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have
been accepted.
Figure 2. Embedded Erase Algorithm
Am29F016
19
AMD [ AMD ]
