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AM29F016-120EC 参数 Datasheet PDF下载

AM29F016-120EC图片预览
型号: AM29F016-120EC
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 2,097,152 ×8位) CMOS 5.0伏只,扇区擦除闪存 [16-Megabit (2,097,152 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 36 页 / 220 K
品牌: AMD [ AMD ]
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Write Operation Status  
Table 6. Write Operation Status  
Status  
DQ7  
DQ7  
0
DQ6  
DQ5  
DQ3  
DQ2  
1
Byte Program in Embedded Program Algorithm  
Embedded Program Algorithm  
Toggle  
Toggle  
0
0
0
1
Toggle  
Erase Suspended Read  
Toggle  
1
1
0
Data  
0
1
Data  
1
(Erase Suspended Sector)  
(Note 1)  
In Progress  
Erase Suspended Read  
Erase Suspended  
Mode  
Data  
DQ7  
Data  
Data  
(Non-Erase Suspended Sector)  
Erase Suspended Read  
1
Toggle  
(Note 2)  
(Non-Erase Suspended Sector)  
(Note 3)  
Byte Program in Embedded Program Algorithm  
DQ7  
0
Toggle  
Toggle  
1
1
0
1
1
Program/Erase Program in Embedded Program Algorithm  
N/A  
Exceeded  
Time Limits  
Erase Suspended Read  
Erase Suspended  
Mode  
DQ7  
Toggle  
1
1
N/A  
(non-Erase Suspended Sector)  
Notes:  
1. Performing successive read operations from the erase-suspended sector will cause DQ2 to toggle.  
2. Performing successive read operations from any address will cause DQ6 to toggle.  
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic ‘1’ at the DQ2 bit.  
However, successive reads from the erase-suspended sector will cause DQ2 to toggle.  
DQ7  
Data Polling  
sequence. For sector erase, the Data Polling is valid  
after the last rising edge of the sector erase WE pulse.  
Data Polling must be performed at sector addresses  
within any of the sectors being erased and not a sector  
that is within a protected sector group. Otherwise, the  
status may not be valid.  
The Am29F016 device features Data Polling as a  
method to indicate to the host that the embedded  
algorithms are in progress or completed. During the  
Embedded Program Algorithm, an attempt to read the  
device will produce the complement of the data last  
written to DQ7. Upon completion of the Embedded  
Program Algorithm, an attempt to read the device will  
produce the true data last written to DQ7. During the  
Embedded Erase Algorithm, an attempt to read the  
device will produce a “0” at the DQ7 output. Upon  
completion of the Embedded Erase Algorithm an at-  
tempt to read the device will produce a “1” at the DQ7  
output. The flowchart for Data Polling (DQ7) is shown  
in Figure 3.  
Just prior to the completion of Embedded Algorithm op-  
erations DQ7 may change asynchronously while the  
output enable (OE) is asserted low. This means that  
the device is driving status information on DQ7 at one  
instant of time and then that byte’s valid data at the next  
instant of time. Depending on when the system sam-  
ples the DQ7 output, it may read the status or valid  
data. Even if the device has completed the Embedded  
Algorithm operations and DQ7 has a valid data, the  
data outputs on DQ0–DQ6 may be still invalid. The  
valid data on DQ0–DQ7 can be read on the successive  
read attempts.  
Data Polling will also flag the entry into Erase Suspend.  
DQ7 will switch “0” to “1” at the start of the Erase Sus-  
pend mode. Please note that the address of an erasing  
sector must be applied in order to observe DQ7 in the  
Erase Suspend Mode.  
The Data Polling feature is only active during the Em-  
bedded Programming Algorithm, Embedded Erase Al-  
gorithm, Erase Suspend, erase-suspend-program  
mode, or sector erase time-out (see Table 6).  
During Program in Erase Suspend, Data Polling will  
perform the same as in regular program execution out-  
side of the suspend mode.  
See Figure 11 for the Data Polling timing specifications  
and diagrams.  
For chip erase, the Data Polling is valid after the rising  
edge of the sixth WE pulse in the six write pulse  
Am29F016  
15  
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