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AM29F016-120EC 参数 Datasheet PDF下载

AM29F016-120EC图片预览
型号: AM29F016-120EC
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 2,097,152 ×8位) CMOS 5.0伏只,扇区擦除闪存 [16-Megabit (2,097,152 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 36 页 / 220 K
品牌: AMD [ AMD ]
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rithm. Upon executing the algorithm, the system is not  
required to provide further controls or timings. The de-  
vice will automatically provide adequate internally gen-  
erated program pulses and verify the programmed cell  
margin.  
then followed by the sector erase command. The sector  
address (any address location within the desired sec-  
tor) is latched on the falling edge of WE, while the com-  
mand (30H) is latched on the rising edge of WE. After  
a time-out of 50 µs from the rising edge of the last sec-  
tor erase command, the sector erase operation will  
begin.  
This automatic programming operation is completed  
when the data on DQ7 (also used as Data Polling) is  
equivalent to the data written to this bit at which time  
the device returns to the read mode and addresses are  
no longer latched (see Table 6, Write Operation Sta-  
tus). Therefore, the device requires that a valid address  
to the device be supplied by the system at this particu-  
lar instance of time for Data Polling operations. Data  
Polling must be performed at the memory location  
which is being programmed.  
Multiple sectors may be erased sequentially by writing  
the six bus cycle operations as described above. This  
sequence is followed with writes of the Sector Erase  
command to addresses in other sectors desired to be  
concurrently erased. The time between writes must be  
less than 50 µs otherwise that command will not be ac-  
cepted and erasure will start. It is recommended that  
processor interrupts be disabled during this time to  
guarantee this condition. The interrupts can be re-en-  
abled after the last Sector Erase command is written. A  
time-out of 50 µs from the rising edge of the last WE will  
initiate the execution of the Sector Erase command(s).  
If another falling edge of the WE occurs within the 50  
µs time-out window the timer is reset. (Monitor DQ3 to  
determine if the sector erase timer window is still open,  
see section DQ3, Sector Erase Timer.) Any command  
other than Sector Erase or Erase Suspend during this  
period will reset the device to the read mode, ignoring  
the previous command string. In that case, restart the  
erase on those sectors and allow them to com-  
plete.(Refer to the Write Operation Status section for  
DQ3, Sector Erase Timer, operation.) Loading the sec-  
tor erase buffer may be done in any sequence and with  
any number of sectors (0 to 31).  
Any commands written to the chip during the Embed-  
ded Program Algorithm will be ignored. If a hardware  
reset occurs during the programming operation, the  
data at that particular location will be corrupted.  
Programming is allowed in any sequence and across  
sector boundaries. Beware that a data “0” cannot be  
programmed back to a “1”. Attempting to do so may ei-  
ther hang up the device or result in an apparent suc-  
cess according to the data polling algorithm but a read  
from reset/read mode will show that the data is still “0”.  
Only erase operations can convert “0”s to “1”s.  
Figure 1 illustrates the Embedded Programming Algo-  
rithm using typical command strings and bus  
operations.  
Chip Erase  
Sector erase does not require the user to program the  
device prior to erase. The device automatically pro-  
grams all memory locations in the sector(s) to be  
erased prior to electrical erase. When erasing a sector  
or sectors the remaining unselected sectors are not af-  
fected. The system is not required to provide any con-  
trols or timings during these operations.  
Chip erase is a six bus cycle operation. There are two  
“unlock” write cycles. These are followed by writing the  
“set-up” command. Two more “unlock” write cycles are  
then followed by the chip erase command.  
Chip erase does not require the user to program the  
device prior to erase. Upon executing the Embedded  
Erase Algorithm command sequence the device will  
automatically program and verify the entire memory for  
an all zero data pattern prior to electrical erase. The  
system is not required to provide any controls or tim-  
ings during these operations.  
The automatic sector erase begins after the 50 µs time  
out from the rising edge of the WE pulse for the last  
sector erase command pulse and terminates when the  
data on DQ7, Data Polling, is “1” (see Write Operation  
Status section) at which time the device returns to the  
read mode. Data Polling must be performed at an ad-  
dress within any of the sectors being erased.  
The automatic erase begins on the rising edge of the  
last WE pulse in the command sequence and termi-  
nates when the data on DQ7 is “1” (see Write Opera-  
tion Status section) at which time the device returns to  
read mode.  
Figure 2 illustrates the Embedded Erase Algorithm  
using typical command strings and bus operations.  
Erase Suspend  
Figure 2 illustrates the Embedded Erase Algorithm  
using typical command strings and bus operations.  
The Erase Suspend command allows the user to inter-  
rupt a Sector Erase operation and then perform data  
reads or programs to a sector not being erased. This  
command is applicable ONLY during the Sector Erase  
operation which includes the time-out period for sector  
erase. The Erase Suspend command will be ignored if  
written during the Chip Erase operation or Embedded  
Sector Erase  
Sector erase is a six bus cycle operation. There are two  
“unlock” write cycles. These are followed by writing the  
“set-up” command. Two more “unlock” write cycles are  
Am29F016  
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